2011
DOI: 10.1149/1.3630820
|View full text |Cite
|
Sign up to set email alerts
|

Cleaning Challenges and Solutions for Advanced Technology Nodes

Abstract: Trends in further scaled CMOS technologies are reviewed with respect to the implications for cleaning and wet processing. Particularly the FEOL processes are being considered such as selective cap removal, pre-epi cleaning and post I/I photo resist removal. For technologies beyond the 15nm, several aspects of wet processing of potential new materials, such as Ge and III-V, and advanced integration schemes are covered.

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1

Citation Types

0
3
0

Year Published

2014
2014
2023
2023

Publication Types

Select...
6
2
2

Relationship

1
9

Authors

Journals

citations
Cited by 10 publications
(5 citation statements)
references
References 12 publications
0
3
0
Order By: Relevance
“…An increase in particle removal efficiency with minimum material loss should be the focus of Ge/SiGe post-CMP cleaning process. 3,191 The use of electrochemical mechanical planarization (eCMP) overcomes the defects such as delamination, erosion, and metal layer peeling due to the high down pressure during CMP. eCMP uses an electrochemical reaction to alter the surface to form a passivation film.…”
Section: Future Aspects Of Post-cmp Cleaningmentioning
confidence: 99%
“…An increase in particle removal efficiency with minimum material loss should be the focus of Ge/SiGe post-CMP cleaning process. 3,191 The use of electrochemical mechanical planarization (eCMP) overcomes the defects such as delamination, erosion, and metal layer peeling due to the high down pressure during CMP. eCMP uses an electrochemical reaction to alter the surface to form a passivation film.…”
Section: Future Aspects Of Post-cmp Cleaningmentioning
confidence: 99%
“…In recent years novel approaches for the nanofabrication of semiconductor devices are being studied. These include integration schemes such as FinFET (beyond Si: optionally adopting a replacement fin process flow), Gate-first approach replacement metal gate (RMG), and novel materials such as germanium and III-V compounds such as InGaAs, GaAs, InP, and InAlAs [1]. The introduction of Ge and short channel structures for CMOS devices has generated interest in terms of advantage in electron and hole mobility's.…”
Section: Introductionmentioning
confidence: 99%
“…These include integration schemes such as FinFET (beyond Si: optionally adopting a replacement fin process flow), Gate-first approach and Gate-last approach replacement metal gate (RMG), and novel materials such as Germanium and III-V elements, e.g. InGaAs, GaAs, InP, and InAlAs [1]. The introduction of Ge for CMOS devices is underway due to the higher electron and hole mobility.…”
Section: Introductionmentioning
confidence: 99%