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The semiconductor industry has followed the Moore's Law for more than 40 years. The concept of scaling based on this law is now approaching the end and to maintain the same scaling concept new routes are being investigated. These new routes are commonly identified as 'More-than-Moore' technologies and the most important of them is 3D-IC integration. By 3D-IC Integration it is possible to put more transistors on the same footprint without the need to shrink transistor sizes. However, as for any new technology, there are many challenges and issues that need to be addressed before moving to high volume manufacturing [1].In this work we present the challenges and required improvements identified for 3D stacking in case of ultra thin devices with TSVs (Thru Silicon Vias). In particular, the challenges related to wafer thinning, flip chip bumping, 3D stacking and packaging.

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A key element for improving 3D stacking reliability is the choice of the right Underfill materials. The Underfill is a specialized adhesive that has the main purposes of locking top and bottom dies; it must fill the gap between bumps and between dies, while reducing the differential movement that would occur during thermal cycling. Traditional underfill processes are based on local dispensing after solder bump reflow (Capillary dispensing), or before flip chip operation with no need of reflow (No Flow Underfill, NUF). In case of 3D stacking, such processes present some limitations: need of a dispensing area (die size increase); material flowing (spacing between dies) and cost (low throughput). After an introduction on typical underfill applications like die-to-package and die-die assembly, we report the work done to assess the properties of several Wafer Applied Underfill (WAUF) materials and their integration in 3D stacking. These materials have been initially applied on silicon wafers in order to assess the minimum achievable thickness and the material uniformity. The wafers have been coated by using different methods: spin coating and film lamination. After this initial assessment, the most promising materials have been used for 3D stacking. The test vehicle used has Cu/Sn μbumps with a pitch of 40μm. The quality of the materials is judged by electrical test, SAM (Surface Acoustic Microscope) and X-SEM (Scanning Electron Microscope).

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