Influence of Si wafer thinning processes on (sub)surface defects

Inoue, Fumihiro; Jourdain, Anne; Peng, Lan; Phommahaxay, Alain; Vos, Joeri De; Rebibis, Kenneth June; Miller, Andy; Sleeckx, Erik; Beyne, Eric; Uedono, Akira

doi:10.1016/j.apsusc.2017.01.259

Cited by 29 publications

(14 citation statements)

References 20 publications

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“…We were finally able to trace the traps to the chemical-mechanical polishing (CMP) process used during thinning. Although defects in CMP-prepared surfaces are difficult to detect, near-surface silicon vacancies have been observed [49][50][51]. One interesting aspect of this change in perspective is an explanation for the fact that the QE of CMP-damaged detectors is stable and amenable to calibration, provided the detector temperature remains stable.…”

Section: Optimization Of Mbe Growth Processes and Surface Passivation...mentioning

confidence: 99%

2D-doped silicon detectors for UV/optical/NIR and x-ray astronomy

Hoenk

Jewell

Kyne

et al. 2022

X-Ray, Optical, and Infrared Detectors for Astronomy X

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In this paper we review the physics and performance of back-illuminated CCDs. Models of back-illuminated CCDs are used to derive requirements for stable, strong surface passivation in space-relevant environments. Models and data are used to compare state-of-the-art surface passivation methods with 2D-doped surfaces. MBE growth of 2D-doped silicon on back-illuminated CCDs and CMOS image sensors enables near 100% charge collection efficiency with exceptional stability in space and other harsh environments. Lifetime tests performed on 2D-doped CMOS image sensors using pulsed DUV lasers have demonstrated the unique stability of 2D-doped detectors against high levels of radiation-induced surface damage. The insensitivity of 2D-doped detectors to Si-SiO2 traps has facilitated the development of a variety of coatings and filters with science-enabling capabilities for NASA instruments and missions in the far and near ultraviolet spectral range. We discuss the status and goals of a strategic partnership between JPL and Teledyne e2v for the certification of 2Ddoping processes, and report initial results from our collaboration.

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Section: Optimization Of Mbe Growth Processes and Surface Passivation...mentioning

confidence: 99%

2D-doped silicon detectors for UV/optical/NIR and x-ray astronomy

Hoenk

Jewell

Kyne

et al. 2022

X-Ray, Optical, and Infrared Detectors for Astronomy X

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“…For this purpose, a "stress relief process" is utilized as a subsequent process after grinding, in particular, when the Si is thinner. Typical candidates used for this stress relief process are polishing [7,27], wet etching [28][29][30][31], and dry etching [5,31]. Although the damage removal of the ground surface has been comprehensively studied [16], the edge trimmed sidewall is not well done.…”

Section: Kailer Et Al Reported That During the Loading Of The Indentmentioning

confidence: 99%

“…Wafer scale three-dimensional integration using direct wafer bonding has been getting extra attention for enhancing system performance in the next generation of electronic devices such as micro-electro-mechanical systems, backside illuminated CMOS image sensors, and heterogeneously stacked devices [1][2][3][4][5]. An alternative integration scheme for these devices is in essence substrate removal till the buried oxide or extreme Si thinning (i.e., few microns of Si) of the top wafer of a bonded wafer pair [4,5]. Wafer thinning has been implemented into the integration flow of completed devices before they are singulated into dies to minimize the assembled package thickness.…”

Section: Introductionmentioning

confidence: 99%

“…Wafer thinning has been implemented into the integration flow of completed devices before they are singulated into dies to minimize the assembled package thickness. The primary method in the Si thinning process is an abrasive diamond process, which includes backside grinding and edge trimming [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. The edge trimming is a diamond abrasive sawing process, which mechanically removes the top wafer edge prior to grinding [18].…”

Section: Introductionmentioning

confidence: 99%

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Edge Trimming Induced Defects on Direct Bonded Wafers

Inoue

Jourdain

Peng

et al. 2018

Journal of Electronic Packaging

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The diamond abrasive process which is applied onto the silicon wafer edge, the so called “edge trimming,” is an important step in three-dimensional microelectronics processing technology, due to the significant thickness reduction of the wafer after thinning. Nevertheless, the wafer edge defects caused by edge trimming have often been overlooked. Although the mechanisms of the formation of the defects in Si due to trimming may be similar to the ones caused by grinding, an in-depth study and risk assessment have not been done yet. In addition, the variety of stress relief processing options can give different morphology and defect removal behavior on the edge trimmed Si sidewall. In a first study, we used transmission electron microscopy and Raman spectroscopy to analyze the defects caused by edge trimming. We show the presence of a continuous layer of amorphous Si and of different phases of Si, caused by edge trimming. A comparison of the damage induced in the Si by two different integration schemes is also discussed. When polishing is used for stress release, the observed sidewall defects stay, since the polishing force is only applied on the top surface of the wafer. On the other hand, the damage is completely removed for the case of wet and dry etching. The surface chemical reactions occurring at the surface during these processes are also acting on the Si sidewall. These findings provide a workable edge trimming and stress relief method for permanently bonded wafers, with many industrial applications.

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“…The subsurface damage introduced in precision machining is often evaluated by destructive methods. The silicon wafers are diced and the microscopic morphology of the cross-section is observed by scanning electron microscopes (SEM) or transmission electron microscopes (TEM) to evaluate the processing quality [7,8]. Gao et al compared the subsurface damage images machined by grinding with those of chemo-mechanical polishing [9].…”

Section: Introductionmentioning

confidence: 99%

Obtainment of Residual Stress Distribution from Surface Deformation under Continuity Constraints for Thinned Silicon Wafers

et al. 2021

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Precision machining (e.g., fine grinding, polishing) induced residual stress is very small and often not constant across the wafer and it is difficult to be directly obtained by stress testing equipment or Stoney equation. The residual stress could be obtained theoretically based on the principle of superposition in which the entire wafer deformation is taken as the sum of all deformations induced by the residual stresses of different positions on the wafer surface. However, the solved residual stress is affected greatly by deformation measurement errors and fluctuates greatly across the wafer surface. To solve the problem, a regularization method with continuity constraints was proposed in this study. The mechanisms for the discontinuity of the residual stress distribution and the sensitivity of calculation results to the measurement errors were studied. The influences of the number of subareas of the silicon wafer were investigated and the continuity constraint term was constructed based on the positional relationship of different subareas. Stable and continuous residual stress distribution was successfully obtained after using the proposed regularization method. The method may also be applied to estimate the residual stress from surface deformation for thin substrate plates of other materials.

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Influence of Si wafer thinning processes on (sub)surface defects

Cited by 29 publications

References 20 publications

2D-doped silicon detectors for UV/optical/NIR and x-ray astronomy

2D-doped silicon detectors for UV/optical/NIR and x-ray astronomy

Edge Trimming Induced Defects on Direct Bonded Wafers

Obtainment of Residual Stress Distribution from Surface Deformation under Continuity Constraints for Thinned Silicon Wafers

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