Hybrid 14nm FinFET - Silicon Photonics Technology for Low-Power Tb/s/mm<sup>2</sup> Optical I/O

Rakowski, Michal; Ban, Yoojin; Heyn, Peter De; Pantano, Nicolas; Snyder, Bradley; Balakrishnan, Sadhishkumar; Huylenbroeck, Stefaan Van; Bogaerts, Lieve; Demeurisse, C.; Inoue, Fumihiro; Rebibis, Kenneth June; Nolmans, P.; Sun, Xin; Bex, Pieter; Srinivasan, Ashwyn; Coster, J. De; Lardenois, S.; Miller, Andy; Absil, P.; Verheyen, Peter; Velenis, Dimitrios; Pantouvaki, Marianna; Campenhout, Joris Van

doi:10.1109/vlsit.2018.8510668

Cited by 34 publications

(18 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Compared to the TW-MZMs, their energy efficiency can be improved by 10-100 times and down to the fJ/bit level [159,160]. Bandwidth densities of over 1 Tb/s/ mm 2 have been demonstrated using WDM MRM hybrids integrated with 14 nm FinFET [161]. In addition, MRMs can work simultaneously as MUX and modulators, thus greatly simplifying WDM transmitters [162,163].…”

Section: Ultracompact Low-power Devicesmentioning

confidence: 99%

Scaling capacity of fiber-optic transmission systems via silicon photonics

2020

View full text Add to dashboard Cite

The tremendous growth of data traffic has spurred a rapid evolution of optical communications for a higher data transmission capacity. Next-generation fiber-optic communication systems will require dramatically increased complexity that cannot be obtained using discrete components. In this context, silicon photonics is quickly maturing. Capable of manipulating electrons and photons on the same platform, this disruptive technology promises to cram more complexity on a single chip, leading to orders-of-magnitude reduction of integrated photonic systems in size, energy, and cost. This paper provides a system perspective and reviews recent progress in silicon photonics probing all dimensions of light to scale the capacity of fiber-optic networks toward terabits-per-second per optical interface and petabits-per-second per transmission link. Firstly, we overview fundamentals and the evolving trends of silicon photonic fabrication process. Then, we focus on recent progress in silicon coherent optical transceivers. Further scaling the system capacity requires multiplexing techniques in all the dimensions of light: wavelength, polarization, and space, for which we have seen impressive demonstrations of on-chip functionalities such as polarization diversity circuits and wavelength- and space-division multiplexers. Despite these advances, large-scale silicon photonic integrated circuits incorporating a variety of active and passive functionalities still face considerable challenges, many of which will eventually be addressed as the technology continues evolving with the entire ecosystem at a fast pace.

show abstract

Section: Ultracompact Low-power Devicesmentioning

confidence: 99%

Scaling capacity of fiber-optic transmission systems via silicon photonics

2020

View full text Add to dashboard Cite

show abstract

“…The most common types of flip chip bumps (FC bumps) are copper pillars and microsolder bumps. Copper pillars between PICs and EICs have been demonstrated with parasitic capacitances below 30 fF, parasitic resistances below 1 Ω, and neglible parasitic inductance [31]. Microsolder bumps between PICs and EICs have been demonstrated with parasitic capacitances below 25 fF and parasitic resistances below 1 Ω [32].…”

Section: D Integrationmentioning

confidence: 99%

“…Microsolder bumps between PICs and EICs have been demonstrated with parasitic capacitances below 25 fF and parasitic resistances below 1 Ω [32]. Microsolder bumps and copper pillars in transceiver MCMs have achieved similarly dense pitches-in the range of 40 µm to 50 µm [31], [32], [33]. Microsolder bumps and copper pillars are expected to be able to reach pitches of 20 µm and 10 µm, respectively [34].…”

Section: D Integrationmentioning

confidence: 99%

“…The energy per bit roughly scales with the EIC technology node. On one end, the 14 nm node EIC transceiver consumes 229 fJ/b [31]; on the other end, the 130 nm node EIC transceiver consumes 11.2 pJ/b [37], [38] While 3D integration allows for dense pitches and minimal packaging parasitics, it does not provide the best approach for thermal dissipation from the EIC and offers minimal thermal isolation between the EIC and PIC. Heat generated by the flip chip assembled EIC can be transferred to the PIC.…”

Section: D Integrationmentioning

confidence: 99%

“…The microdisk modulator occupies approximately 250 µm 2 and the combination of the microdisk demux and high-speed photodiode occupies approximately 750 µm 2 . The small microdisk footprints allows transceivers to designed very densely and to still achieve system data rates in the Tbps regime [31]. Additionally, microdisk modulators have lower device capacitances and typically require smaller swing voltages compared to Mach Zehnder modulators [58], allowing the microdisk modulators to consume less modulation power.…”

Section: A Photonic Architecturementioning

confidence: 99%

See 2 more Smart Citations

Silicon Photonic 2.5D Multi-Chip Module Transceiver for High-Performance Data Centers

Abrams

Cheng

Glick

et al. 2020

J. Lightwave Technol.

View full text Add to dashboard Cite

Widespread adoption of silicon photonics into datacenters requires that the integration of the driving electronics with the photonics be an essential component of transceiver development. In this article, we describe our silicon photonic transceiver design: a 2.5D integrated multi-chip module (MCM) for 4-channel wavelength division multiplexed (WDM) microdisk modulation targeting 10 Gbps per channel. A silicon interposer is used to provide connectivity between the photonic integrated circuit (PIC) and the commercial transimpedance amplifiers (TIAs). Error free modulation is demonstrated at 10 Gbps with −16 dBm received power for the photonic bare die and at 6 Gbps with −15 dBm received power for the first iteration of the MCM transceiver. In this context, we outline the different integration approaches currently being employed to interface between electronics and photonicsmonolithic, 2D, 3D, and 2.5D-and discuss their tradeoffs. Notable demonstrations of the various integration architectures are highlighted. Finally, we address the scalability of the architecture and highlight a subsequent prototype employing custom electronic integrated circuits (EICs).

show abstract

Photonic-integrated circuit fabrication and test approaches

Jacob¹,

Chandran²,

Campenhout³

et al. 2023

Integrated Photonics for Data Communication Applications

View full text Add to dashboard Cite

Hybrid 14nm FinFET - Silicon Photonics Technology for Low-Power Tb/s/mm² Optical I/O

Cited by 34 publications

References 6 publications

Scaling capacity of fiber-optic transmission systems via silicon photonics

Scaling capacity of fiber-optic transmission systems via silicon photonics

Silicon Photonic 2.5D Multi-Chip Module Transceiver for High-Performance Data Centers

Photonic-integrated circuit fabrication and test approaches

Contact Info

Product

Resources

About

Hybrid 14nm FinFET - Silicon Photonics Technology for Low-Power Tb/s/mm2 Optical I/O

Cited by 34 publications

References 6 publications

Scaling capacity of fiber-optic transmission systems via silicon photonics

Scaling capacity of fiber-optic transmission systems via silicon photonics

Silicon Photonic 2.5D Multi-Chip Module Transceiver for High-Performance Data Centers

Photonic-integrated circuit fabrication and test approaches

Contact Info

Product

Resources

About

Hybrid 14nm FinFET - Silicon Photonics Technology for Low-Power Tb/s/mm² Optical I/O