Thermo-mechanical impact of the underfill-microbump interaction in 3D stacked integrated circuits

Ivankovic, A.; Vandevelde, Bart; Rebibis, Kenneth June; Manna, A. La; Plas, G. Van der; Cherman, Vladimir; Beyne, Eric; Wolf, Ingrid De; Vandepitte, Dirk

doi:10.1109/eptc.2011.6184381

Cited by 12 publications

(7 citation statements)

References 4 publications

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“…A tangential tension stress and a radial compression stress could be built-in the Si at µbump proximity as showing in the figure 6 (a). The figure 6 (b) shows the FEM simulation result 978-1-4673-0145-9/12/$31.00 ©2012 IEEE depicting the behavior of the die to die stack in the µbump region after structures cooling from bonding temperature (250ºC) to room temperature [5]. In case of several µbump arrays a wavelike pattern can be expected on the top thin Si die as showed in figure 6 (c) [6].…”

Section: B µBump Induced Stress On Thinned Si Diementioning

confidence: 92%

“…[4][5][6][7][8] Figure 7 (a) illustrates the Fammos simulation results of TSV induced stress components projected on orthogonal axes versus distance from device center to TSV center [8]. For a device with current flowing at horizontal direction as shown on figure 5, the stress component at x direction σ XX is a positive tensile stress and σ YY at y direction is a negative compressive stress.…”

Section: B µBump Induced Stress On Thinned Si Diementioning

confidence: 99%

“…Figure 6. Simulated bending of the top thin Si die after stack cooling from bonding temperature [5,6].…”

Section: B µBump Induced Stress On Thinned Si Diementioning

confidence: 99%

“…By using a combined experimental and theoretical approach, we provided a framework that will enable stress-aware design and the right definition of keep-out-zone which ultimately saves valuable silicon area [4]. The stress induced by µ-bumps technology also greatly influence the performance of FEOL devices [5,6] and this significant contribution is analyzed in section IV. The via-middle Cu TSVs approach and die to die stacking options are described in Figure 2.…”

Section: Introductionmentioning

confidence: 99%

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3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps

Guo

Plas

Ivankovic

et al. 2012

2012 IEEE International Conference on IC Design &Amp; Technology

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The 3D IC stacking technology with Through Silicon via (TSV) approach promises lower cost, smaller footprint and higher performance for heterogeneous system integration. 3D integration technology needs key components to be enabled: Like TSV technology, Wafer thinning, thin wafer carrier and handling technology and µbumps interconnects. In the via-middle 3D-Stacked IC approach, Cu filled TSVs are integrated after device fabrication and before metal 1. The stress patterns around TSV's and µbumps are considered as important concerns for 3D integration, as this leads to additional variability in MOSFET mobility, threshold voltage, and drivability. This contribution reviews the assessment of TSV and µbumps proximity effects on FEOL device performance.

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Section: B µBump Induced Stress On Thinned Si Diementioning

confidence: 92%

Section: B µBump Induced Stress On Thinned Si Diementioning

confidence: 99%

“…Figure 6. Simulated bending of the top thin Si die after stack cooling from bonding temperature [5,6].…”

Section: B µBump Induced Stress On Thinned Si Diementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps

Guo

Plas

Ivankovic

et al. 2012

2012 IEEE International Conference on IC Design &Amp; Technology

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“…Bumps, consisting of intermetallic compounds (in the case of FC bumps) or copper (micro-bumps), are characterized by the substantially larger Young's modulus (E b ) than the underfill material (E u ), i.e., E b > E u , but by smaller CTE (i.e., α b < α u ). As a result, the placement of the bump into the underfill layer should modify the warpage-related displacement fields both in lateral (x; y) and vertical (z) directions 13 (Fig. 4).…”

Section: Compact Model For Bump-induced Displacementsmentioning

confidence: 99%

Stress assessment for device performance in three-dimensional IC: linked package-scale/die-scale/feature-scale simulation flow

Kteyan¹,

Gevorgyan²,

Hovsepyan³

et al. 2014

J. Micro/Nanolith. MEMS MOEMS

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Abstract. Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3-D) IC technologies are outlined. The growing need in a simulation-based design verification flow capable of analyzing a design of 3-D IC stacks and detecting acrossdie out-of-spec variations in MOSFET electrical characteristics caused by the die thinning and stacking-induced mechanical stress is addressed. The development of a multiscale simulation methodology for managing mechanical stresses during a sequence of designs of 3-D IC dies, stacks, and packages is focused. A set of physics-based compact models for a multiscale simulation is proposed to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 2.5D interposer-based, and true 3-D through silicon via-based technology. A simulation flow is developed for the hot-spot checking in different types of devices/circuits such as digital, analog, analog matching, memory, IO, characterized by different sensitivities to the stress-induced mobility variations. A calibration technique based on fitting to measured electrical characteristics of the test-chip devices is presented. The limited characterization or measurement capabilities for 3-D IC stacks and a strict "good die" requirement make this type of analysis critical in order to achieve an acceptable level of functional and parametric yield. © The Authors. Published by SPIE under a Creative Commons Attribution 3.0 Unported License. Distribution or reproduction of this work in whole or in part requires full attribution of the original publication, including its DOI.

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Multi-scale simulation flow and multi-scale materials characterization for stress management in 3D through-silicon-via integration technologies – Effect of stress on 3D IC interconnect reliability

Sukharev¹,

Zschech²

2014

AIP Conference Proceedings

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Thermo-mechanical impact of the underfill-microbump interaction in 3D stacked integrated circuits

Cited by 12 publications

References 4 publications

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps

Stress assessment for device performance in three-dimensional IC: linked package-scale/die-scale/feature-scale simulation flow

Multi-scale simulation flow and multi-scale materials characterization for stress management in 3D through-silicon-via integration technologies – Effect of stress on 3D IC interconnect reliability

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Thermo-mechanical impact of the underfill-microbump interaction in 3D stacked integrated circuits

Cited by 12 publications

References 4 publications

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and &#x03BC;-bumps

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and &#x03BC;-bumps

Stress assessment for device performance in three-dimensional IC: linked package-scale/die-scale/feature-scale simulation flow

Multi-scale simulation flow and multi-scale materials characterization for stress management in 3D through-silicon-via integration technologies – Effect of stress on 3D IC interconnect reliability

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Product

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3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps