A novel physical model and a simulation algorithm are used to predict electromigration (EM)-induced stress evolution in dual inlaid copper interconnects. The aim of the current simulation was to investigate the dual effect of the microstructure, which consists of the effect of grain boundaries (GBs) and the effect of texture-related variations of the modulus of elasticity on the stress evolution in copper lines caused by EM. The major difference between our approach and the previously described ones is the accounting of additional stress generated by the plated atoms. The results of the numerical simulation have been proven experimentally by EM degradation studies on fully embedded dual inlaid copper interconnect test structures and by subsequent microstructure analysis, mainly based on electron backscatter diffraction (EBSD) data. The virtual EM-induced void formation, movement, and growth in a copper interconnect were continuously monitored in an in situ scanning electron microscopy experiment. The copper microstructure, particularly the orientation of grains and GBs, was determined with EBSD. For interconnects with interfaces that resist atomic transport and where GBs are the important pathways for atom migration, degradation and failure processes are completely different for microstructures with randomly oriented GBs compared with "bamboolike" microstructures. The correspondence between simulation results and experimental data indicates the applicability of the developed model for optimization of the physical and electrical design rules.
A novel model-based algorithm provides a capability to control full-chip design-specific variation in pattern transfer caused by via/ contact etch ͑VCE͒ processes. This physics-based algorithm is capable of detecting and reporting etch hot spots based on the fabricationdefined thresholds of acceptable variations in critical dimension ͑CD͒ of etched shapes. It can be used also as a tool for etch process optimization to capture the impact of a variety of patterns presented in a particular design. A realistic set of process parameters employed by the developed model allows using this novel VCE electronic design automation tool for design-aware process optimization in addition to the "standard" process-aware design optimization. Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 05/16/2015 Terms of Use: http://spiedl.org/terms Sukharev et al.: Design specific variation in pattern transfer by via/contact… J. Micro/Nanolith. MEMS MOEMS Oct-Dec 2009/Vol. 8͑4͒ 043007-2 Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 05/16/2015 Terms of Use: http://spiedl.org/terms Sukharev et al.: Design specific variation in pattern transfer by via/contact… J. Micro/Nanolith. MEMS MOEMS Oct-Dec 2009/Vol. 8͑4͒ 043007-3 Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 05/16/2015 Terms of Use: http://spiedl.org/terms Sukharev et al.: Design specific variation in pattern transfer by via/contact… J. Micro/Nanolith. MEMS MOEMS Oct-Dec 2009/Vol. 8͑4͒ 043007-11 Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 05/16/2015 Terms of Use: http://spiedl.org/terms Sukharev et al.: Design specific variation in pattern transfer by via/contact… J.
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