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This paper proposes new pathological element-based active device models which can be used in analysis tasks of linear(ized) analog circuits. Nullators and norators along with the Voltage Mirror-Current Mirror (VM-CM) pair (collectively known as pathological elements) are used to model the behavior of active devices in voltage-, current-and mixed-mode, also considering parasitic elements. Since analog circuits are transformed to nullor-based equivalent circuits or VM-CM pairs or as a combination of both, standard nodal analysis can be used to formulate the admittance matrix. We present a formulation method in order to build the Nodal Admittance (NA) matrix of nullor-equivalent circuits, where the order of the matrix is given by the number of nodes minus the number of nullors. Since pathological elements are used to model the behavior of active devices, we introduce a more efficient formulation method in order to compute small-signal characteristics of pathological element-based equivalent circuits, where the order of the NA matrix is given by the number of nodes minus the number of pathological elements. Examples are discussed in order to illustrate the potential of the proposed pathological elementbased active device models and the new formulation method in performing symbolic analysis of analog circuits. The improved formulation method is compared with traditional formulation methods, showing that the NA matrix is more compact and the generation of non-zero coefficients is reduced. As a consequence, the proposed formulation method is the most efficient one reported so far, since the CPU-time and memory consumption is reduced when recursive determinant-expansion techniques are used to solve the NA matrix.

Model order reduction (MOR) techniques reduce the complexity of VLSI designs, paving the way to higher operating speeds and smaller feature sizes. This 2007 book presents a systematic introduction to, and treatment of, the key MOR methods employed in general linear circuits, using real-world examples to illustrate the advantages and disadvantages of each algorithm. Following a review of traditional projection-based techniques, coverage progresses to more advanced MOR methods for VLSI design, including HMOR, passive truncated balanced realization (TBR) methods, efficient inductance modeling via the VPEC model, and structure-preserving MOR techniques. Where possible, numerical methods are approached from the CAD engineer's perspective, avoiding complex mathematics and allowing the reader to take on real design problems and develop more effective tools. With practical examples and over 100 illustrations, this book is suitable for researchers and graduate students of electrical and computer engineering, as well as practitioners working in the VLSI design industry.

Abstract-A graph-based approach is presented for the generation of exact symbolic network functions in the form of rational polynomials of the complex frequency variable for analog integrated circuits. The approach employs determinant decision diagrams (DDDs) to represent the determinant of a circuit matrix and its cofactors. A notion of multiroot DDDs is introduced, where each root represents a symbolic expression for an individual coefficient of the powers of in the numerator and denominator of a network function, and multiple roots share their common subgraphs. A DDD-based algorithm is presented for generating -expanded network functions. We prove theoretically and validate experimentally that the algorithm constructs in ( DDD ) time an -expanded DDD with no more than DDD vertices, where is the degree of the denominator polynomial, is the maximum number of devices that connect to a circuit node, and DDD is the number of DDD vertices representing the circuit-matrix determinant. For a practical circuit, DDD is often many orders-ofmagnitude less than the number of product terms. In contrast, previous approaches require the time and space complexities proportional to the number of product terms, which grows exponentially with the size of a circuit. Experimental results have demonstrated that the new approach can produce exact -expanded-symbolic network functions for A741 operational amplifiers in several CPU seconds on an UltraSparc-I workstation. The expressive power of multiroot -expanded DDDs is so remarkable that in one instance, over 10 35 symbolic product terms have been represented by a multiroot DDD with less than 17 K vertices. The compactness of DDDs is further demonstrated in the context of symbolic noise evaluation, where potentially many transfer functions, each being used for a noise source in the circuit, can be represented by a single DDD with the size comparable to that for a few transfer functions. This provides a powerful tool for solving many symbolic analysis problems such as deriving interpretable symbolic expressions, dominant pole/zero estimation, and analog testability analysis. We have also demonstrated that repetitive numerical evaluation with the derived -expanded symbolic expressions for frequency-domain simulation and small-signal noise analysis can be much faster than SPICE-like simulators and the resulting expressions for a circuit block can be used as behavioral models for high-level simulation.

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