Sundry mevalonate-derived constituents (isoprenoids) of fruits, vegetables and cereal grains suppress the growth of tumors. This study estimated the concentrations of structurally diverse isoprenoids required to inhibit the increase in a population of murine B16(F10) melanoma cells during a 48-h incubation by 50% (IC50 value). The IC50 values for d-limonene and perillyl alcohol, the monoterpenes in Phase I trials, were 450 and 250 micromol/L, respectively; related cyclic monoterpenes (perillaldehyde, carvacrol and thymol), an acyclic monoterpene (geraniol) and the end ring analog of beta-carotene (beta-ionone) had IC50 values in the range of 120-150 micromol/L. The IC50 value estimated for farnesol, the side-chain analog of the tocotrienols (50 micromol/L) fell midway between that of alpha-tocotrienol (110 micromol/L) and those estimated for gamma- (20 micromol/L) and delta- (10 micromol/L) tocotrienol. A novel tocotrienol lacking methyl groups on the tocol ring proved to be extremely potent (IC50, 0.9 micromol/L). In the first of two diet studies, experimental diets were fed to weanling C57BL female mice for 10 d prior to and 28 d following the implantation of the aggressively growing and highly metastatic B16(F10) melanoma. The isomolar (116 micromol/kg diet) and the Vitamin E-equivalent (928 micromol/kg diet) substitution of d-gamma-tocotrienol for dl-alpha-tocopherol in the AIN-76A diet produced 36 and 50% retardations, respectively, in tumor growth (P < 0.05). In the second study, melanomas were established before mice were fed experimental diets formulated with 2 mmol/kg d-gamma-tocotrienol, beta-ionone individually and in combination. Each treatment increased (P < 0.03) the duration of host survival. Our finding that the effects of individual isoprenoids were additive suggests the possibility that one component of the anticarcinogenic action of plant-based diets is the tumor growth-suppressive action of the diverse isoprenoid constituents of fruits, vegetables and cereal grains.

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This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contributions: (i) We develop a mixed-level FPGA power model that combines switch-level models for interconnects and macromodels for LUTs; (ii) We develop a tool that automatically generates a back-annotated gate-level netlist with post-layout extracted capacitances and delays; (iii) We develop a cycleaccurate power simulator based on our power model. It carries out gate-level simulation under real delay model and is able to capture glitch power; (iv) Using the framework fpgaEVA-LP, we study the power efficiency of FPGAs, in 0.10um technology, under various settings of architecture parameters such as LUT sizes, cluster sizes and wire segmentation schemes and reach several important conclusions. We also present the detailed power consumption distribution among different FPGA components and shed light on the potential opportunities of power optimization for future FPGA designs (e.g., ≤ 0.10um technology).

Increased variability of process parameters and recent progress in statistical static timing analysis make extraction of statistical characteristics of process variation and spatial correlation an important yet challenging problem in modern chip designs. Unfortunately, existing approaches either focus on extraction of only a deterministic component of spatial variation or do not consider actual difficulties in computing a valid spatial correlation function and matrix, simply ignoring the fact that not every function and matrix can be used to describe the spatial correlation. Based upon the mathematical theory of random fields and convex analysis, in this paper, we develop (1) a robust technique to extract a valid spatial correlation function by solving a constrained nonlinear optimization problem; and (2) a robust technique to extract a valid spatial correlation matrix by employing a modified alternative projection algorithm. Our novel techniques guarantee to extract a valid spatial correlation function and matrix that are closest to measurement data, even if those measurements are affected by unavoidable random noises. Experiment results based upon a Monte-Carlo model confirm the accuracy and robustness of our techniques, and show that we are able to recover the correlation function and matrix with very high accuracy even in the presence of significant random noises.

In this paper, we first show that existing net ordering formulations to minimize noise are no longer valid with presence of inductive noise, and shield insertion is needed to minimize inductive noise. We then formulate two simultaneous shield insertion and net ordering (SINO) problems: the optimal SINO/NF problem to find a min-area SINO solution that is free of capacitive and inductive noise, and the optimal SINO/NB problem to find a min-area SINO solution that is free of capacitive noise and is under the given inductive noise bound. We reveal that both optimal SINO problems are NP-hard, and propose effective approximate algorithms for the two problems. Experiments show that our SINO/NB algorithm uses from 15% to 57% fewer shield wires when compared to separated net ordering and shield insertion procedure. Furthermore, under practical noise bounds, the SINO/NB solutions use from 44% to 67% fewer shield wires when compared to SINO/NF solutions, and use 10% to 40% fewer shield wires when compared to the theoretical lower bound for optimal SINO/NF solutions. Additionally, all our algorithms are extremely efficient to finish all examples in a few seconds. To the best of our knowledge, it is the first work that presents an indepth study on the simultaneous shield insertion and net ordering problem to minimize both capacitive and inductive noise.

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Abstract

Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the simultaneous switching current per cluster and then inserting a sleep transistor per cluster. In the paper, we propose a novel distributed sleep transistor network (DSTN), and show that DSTN is intrinsically better than the clusterbased design in terms of the sleep transistor area and circuit performance. We reveal properties of optimal DSTN designs, and then develop an efficient algorithm for gate level DSTN synthesis. The algorithm obtains DSTN designs with up to 70.7% sleep transistor area reduction compared to cluster-based designs. Furthermore, we present custom layout designs to verify the area reduction by DSTN.