Architecture evaluation for power-efficient FPGAs

Abstract

This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contributions: (i) We develop a mixed-level FPGA power model that combines switch-level models for interconnects and macromodels for LUTs; (ii) We develop a tool that automatically generates a back-annotated gate-level netlist with post-layout extracted capacitances and delays; (iii) We develop a cycleaccurate power simulator based on our power model. It carries out gate-level simulation under real delay model and is able to capture glitch power; (iv) Using the framework fpgaEVA-LP, we study the power efficiency of FPGAs, in 0.10um technology, under various settings of architecture parameters such as LUT sizes, cluster sizes and wire segmentation schemes and reach several important conclusions. We also present the detailed power consumption distribution among different FPGA components and shed light on the potential opportunities of power optimization for future FPGA designs (e.g., ≤ 0.10um technology).

An Overview of Low-Power Techniques for Field-Programmable Gate Arrays

“…In [36], a similar FPGA power model estimates static and dynamic FPGA power by calculating the power for each clock cycle using simulated switching activity information, instead of vectorless techniques. This power model has been enhanced to support FPGAs with a programmable supply voltage [37] and programmable threshold voltages [38].…”

Register binding and port assignment for multiplexer optimization

“…To get an idea of how the MUX reduction influences the final design in area, delay and power, we feed two of the RT-level designs generated by k-cofamily+pa and bipartite w/o pa to a FPGA design/architecture evaluation framework, fpgaEva_LP [4]. Please note that we target FPGA applications because we have access to the tool.…”

“…where N mux is the number of MUXes saved (or MUXes wasted, i.e., N mux becoming negative) by binding v i and v j into a single register (Case 2) than not binding them into a single register (Case 1); T r_f is the total number of connections between register R1/R2 and the fanout_FUs; T fu is the total number of fanout_FUs involved during this tempted binding of v i and v j ; L is a large positive constant 4 ; α and β are positive scaling constants. The term T r_f is trying to capture the overall connectivity situation of the fanout_FUs so that some global optimization criteria can be considered.…”

“…The smaller the cost, the better to bind v i and v j together. 4 L guarantees w ij < -1 (check the formulation of d(e)). …”

“…This is especially the case for FPGA designs because a larger amount of transistors have to be provided in the wiring channels and logic blocks to provide programmability for signal transition. Studies show that interconnects alone contribute 70-80% of the total area [2] and 75-85% of the total power [3] [4] for most of the FPGA designs.…”