Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics

Li, Fēi; Lin, Yan; He, Lei; Cong, Jason

doi:10.1145/968280.968288

Cited by 137 publications

(91 citation statements)

References 33 publications

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“…This can be achieved by using the dual threshold voltage transistor FPGA routing design [24][25][26]. In this technique, high threshold voltage is applied to one subset of multiplexer transistors and low threshold voltage to the rest of the transistors.…”

Section: Leakage Power Reductionmentioning

confidence: 99%

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Singh¹

2017

Field - Programmable Gate Array

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The design of low-power SRAM cell becomes a necessity in today's FPGAs, because SRAM is a critical component in FPGA design and consumes a large fraction of the total power. The present chapter provides an overview of various factors responsible for power consumption in FPGA and discusses the design techniques of low-power SRAMbased FPGA at system level, device level, and architecture levels. Finally, the chapter proposes a data-aware dynamic SRAM cell to control the power consumption in the cell. Stack effect has been adopted in the design to reduce the leakage current. The various peripheral circuits like address decoder circuit, write/read enable circuits, and sense amplifier have been modified to implement a power-efficient SRAM-based FPGA.

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Section: Leakage Power Reductionmentioning

confidence: 99%

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Singh¹

2017

Field - Programmable Gate Array

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“…In [36], a similar FPGA power model estimates static and dynamic FPGA power by calculating the power for each clock cycle using simulated switching activity information, instead of vectorless techniques. This power model has been enhanced to support FPGAs with a programmable supply voltage [37] and programmable threshold voltages [38]. In [13][25] [52], high-level FPGA power models that use macro-models to estimate power are described.…”

Section: Fpga Power Modellingmentioning

confidence: 99%

An Overview of Low-Power Techniques for Field-Programmable Gate Arrays

Lamoureux

Luk

2008

2008 NASA/ESA Conference on Adaptive Hardware and Systems

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“…Previously, techniques to reduce the static leakage current in FPGAs were aggressively examined. It is shown in [2] that the look-up-table (LUT) leakage is reduced by setting a higher threshold voltage (Vt) to static random access memories (SRAMs). In [3], various low-leakage techniques, such as redundant SRAM design, dual Vt design, body biasing and gate biasing, are evaluated.…”

Section: Introductionmentioning

confidence: 99%

SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability

Hioki

Kobayashi

et al. 2014

JLPEA

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Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is the reduction of its static leakage power consumption. Flex Power FPGA, which has been proposed to overcome this problem, uses a body biasing technique to implement the fine-grained threshold voltage (Vt) programmability in the FPGA. A low-Vt state can be assigned only to the component circuits along the critical path of the application design mapped on the FPGA, so that the static leakage power consumption can be reduced drastically. Flex Power FPGA is an important application target for the SOTB OPEN ACCESSJ. Low Power Electron. Appl. 2014, 4 189(silicon on thin buried oxide) device, which features a wide-range body biasing ability and the high sensitivity of Vt variation by body biasing, resulting in a drastic subthreshold leakage current reduction caused by static leakage power. In this paper, the Flex Power FPGA test chip is fabricated in SOTB technology, and the functional test and performance evaluation of a mapped 32-bit binary counter circuit are performed successfully. As a result, a three orders of magnitude static leakage reduction with a bias range of 2.1 V demonstrates the excellent Vt controllability of the SOTB transistors, and the 1.2 V bias difference achieves a 50× leakage reduction without degrading speed.Keywords: field programmable gate array (FPGA); static leakage power reduction; fine-grained body biasing; silicon on thin buried oxide (SOTB)

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Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics

Abstract: Abstract

Cited by 137 publications

References 33 publications

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

An Overview of Low-Power Techniques for Field-Programmable Gate Arrays

SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability

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