A new method for improving the timing yield of fieldprogrammable gate array (FPGA) devices affected by random within-die variation is proposed. By selection of an appropriate configuration from a set of functionally equivalent configurations such that the critical paths do not share same circuit resources on the FPGA, both the average critical path delay and its standard deviation are reduced substantially under conditions of large random variation. Large within-die variations of device parameters such as transistor threshold voltage are anticipated in future semiconductor technologies, resulting in degradation of parametric yields. Comparing to the previous approach which compensates for such within-die variation by designing circuit placement for each chip using variation information measured before, our method does not require the measurement of process variations and execution of design tools for each chip. The average critical path delay is reduced by up to 5% assuming 30% (σ/μ) variation in threshold voltage, with a corresponding 50% decrease in standard deviation.
Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is the reduction of its static leakage power consumption. Flex Power FPGA, which has been proposed to overcome this problem, uses a body biasing technique to implement the fine-grained threshold voltage (Vt) programmability in the FPGA. A low-Vt state can be assigned only to the component circuits along the critical path of the application design mapped on the FPGA, so that the static leakage power consumption can be reduced drastically. Flex Power FPGA is an important application target for the SOTB OPEN ACCESSJ. Low Power Electron. Appl. 2014, 4 189(silicon on thin buried oxide) device, which features a wide-range body biasing ability and the high sensitivity of Vt variation by body biasing, resulting in a drastic subthreshold leakage current reduction caused by static leakage power. In this paper, the Flex Power FPGA test chip is fabricated in SOTB technology, and the functional test and performance evaluation of a mapped 32-bit binary counter circuit are performed successfully. As a result, a three orders of magnitude static leakage reduction with a bias range of 2.1 V demonstrates the excellent Vt controllability of the SOTB transistors, and the 1.2 V bias difference achieves a 50× leakage reduction without degrading speed.Keywords: field programmable gate array (FPGA); static leakage power reduction; fine-grained body biasing; silicon on thin buried oxide (SOTB)
In this paper, more than an order of magnitude (1/13) energy improvement of FPGA by combining low voltage operation and fine-grained body bias optimization is demonstrated from the measurement of the new SOTB implementation of Flex Power FPGA test chip. (keywords: minimum energy operation, FPGA, static power rediction, body biasing, SOTB and ET-SOI) IntroductionSub-threshold or near-threshold minimum energy operation of logic circuits is a new design paradigm in the post-scaling era. By minimizing the energy per operation (power-delay product) of the circuit, we can fully maximize the total amount of operations squeezed from the limited amount of energy, such as a battery, as long as the operating frequency meets the requirement of the application such as a sensor node. The dynamic energy consumption per operation can be reduced by lowering VDD, while static energy consumption per cycle gradually increases because of the prolonged cycle time. This trade-off determines the minimum energy point (MEP) of the circuit, which is typically around 0.4V. Minimum energy operation of FPGA is particularly complicated because of the relatively high static power consumption by FPGAs. MEP of FPGA tends to be higher than ordinary logic circuits, and energy improvement is substantially limited.Flex Power FPGA [1] uses body biasing technique to implement the fine-grained Vt programmability of the FPGA component circuits such as Look Up Table (LUT) and Multiplexer (MUX), so that Multi-Vt optimization technique can be also applied to FPGAs. Low-Vt state is assigned only to the components along the critical path of the user application design, while High-Vt state is assigned to the most part of the FPGA. As a result, drastic reduction of the static power consumption without speed degradation can be realized. The recent implementation of Flex Power FPGA using SOTB (Silicon On Thin BOX) transistors presented in this conference last year [2, 3] exhibits 1/50 static power reduction performance owing to the excellent Vt controllability of SOTB device. This paper introduces a new version of the Flex Power FPGA test chip. The new chip can operate down to 0.4V this time, owing to the good SOTB performance, the careful circuit design and the new low voltage operation cell libraries. From the measurement results of the test chip, more than an order of magnitude energy improvement of FPGA by combining low voltage operation and fine-grained body bias optimization is demonstrated for the first time.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.