Performance and yield enhancement of FPGAs with within-die variation using multiple configurations

Abstract

A new method for improving the timing yield of fieldprogrammable gate array (FPGA) devices affected by random within-die variation is proposed. By selection of an appropriate configuration from a set of functionally equivalent configurations such that the critical paths do not share same circuit resources on the FPGA, both the average critical path delay and its standard deviation are reduced substantially under conditions of large random variation. Large within-die variations of device parameters such as transistor threshold voltage are anticipated in future semiconductor technologies, resulting in degradation of parametric yields. Comparing to the previous approach which compensates for such within-die variation by designing circuit placement for each chip using variation information measured before, our method does not require the measurement of process variations and execution of design tools for each chip. The average critical path delay is reduced by up to 5% assuming 30% (σ/μ) variation in threshold voltage, with a corresponding 50% decrease in standard deviation.

Improved delay measurement method in FPGA based on transition probability

“…these techniques can be employed to measure delay variability [17] and timing degradation [14] in the latest generation of FPGAs. These test methods concerning the unique delay mapping of circuits in FPGAs are also essential to hardware security schemes such as Physical Unclonable Function (PUF) [7], as well as delay-aware placement and routing methods [5,3,9,13] that provide promising solutions against process variability in FPGAs to improve reliability.…”

FPGA Architecture: Survey and Challenges

“…Proposals include introducing statistical static timing analysis (SSTA) to FPGA CAD tools to improve delays by avoiding the margins that are necessary for traditional static timing analysis [177,184], testing multiple logically equivalent configurations of the FPGA to find one that is functional at the desired speed [177], generating critical paths that will be more robust in the face of variation [147] or customizing the implementation on the FPGA for the variations of each specific device [57,111]. With the increased impact of variability that is expected in future process generations, it is likely a combination of architectural and circuit-level changes will be needed in conjunction with a number of CAD tool innovations.…”

Process variation aware thread mapping for Chip Multiprocessors

“…An analytical modeling approach [16], based on understanding different power and variation sensitivities, is developed to obtain the power reduction benefits. A method of addressing within-die process variation in the routing of FPGAs is presented in [25]. Past work also proposes a process-tolerant cache architecture [9] and studies process variation aware cache leakage management [22].…”

“…In comparison, [11] and [9] focus on profit and yield, respectively. Power improvement is studied in [22], [19], [16], and FPGA is studied in [25]. In addition, most of the above papers are not targeted at chip multiprocessors.…”