3D IC TSV-Based Technology: Stress Assessment For Chip Performance

Sukharev, Valeriy; Kteyan, Armen; Khachatryan, Nikolay; Hovsepyan, Henrik; Torres, J. Andres; Choy, Jun‐Ho; Markosian, Ara

doi:10.1063/1.3527127

Cited by 12 publications

(11 citation statements)

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“…simulations will consider the manufacturing processes-induced thermo-mechanical stress effects on transistor performance and interconnect stack reliability [1,2]. To accurately simulate the stress-induced phenomena, the models require accurate materials data at multiple scales.…”

Section: Introductionmentioning

confidence: 99%

Nanometer deformation of elastically anisotropic materials studied by nanoindentation

Yeap

Kopycinska-Müller

Hangen

et al. 2012

Philosophical Magazine

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The reduced modulus, E-R, of elastically anisotropic materials (Si, CaF2 and MgF2) was determined for sub-10 nm, several-10 nm and several-100 nm indentation depths, applying the Hertzian and Oliver-Pharr approaches. The E-R values determined for Si(100), Si(111), CaF2(100) and MgF2(100) deforming at sub-10 nm indentations (i.e. 135 GPa, 177 GPa, 142 GPa and 168 GPa) are in good agreement with the theoretical unidirectional E-R values (i.e. 125 GPa, 173 GPa, 135 GPa, 160 GPa). With increasing penetration depth up to several-10 nm, the E-R values gradually deviate from the unidirectional values to the weighted averaged values. E-R remains constant for sub-10 nm and several-10 nm penetration depths, performing the same indentation tests on amorphous organosilicate glass. The results of this study indicate that the modulus determined by nanoindentation depends on the size of indentation (ratio between contact radius and tip radius, a/R), especially in the case of elastically anisotropic materials. It is demonstrated for several-10 nm and several-100 nm penetration depth that the phase transformations in Si during the indentation tests strongly affect the E-R values

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Section: Introductionmentioning

confidence: 99%

Nanometer deformation of elastically anisotropic materials studied by nanoindentation

Yeap

Kopycinska-Müller

Hangen

et al. 2012

Philosophical Magazine

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“…A correspondence between the longitudinal stresses calculated with COMSOL FEA tool (left) and with the developed approximate calculation methodology (right) [11]. Figure 6 demonstrates an agreement between the package-induced longitudinal stress calculated with the COMSOL FEA code and with the described compact model.…”

Section: Figurementioning

confidence: 87%

“…This saturation distance, which is the radius of interaction, depends on the type of the stressor. It was shown that for 45 nm technology node the saturation distance is about 1 m for the CESL, 4 m for Si 1-x Ge x , and 5 m for STI [11]. This observation makes the simulation of stress relaxation much easier.…”

Section: Simulation Of the Transistor Intrachannel Stress Componentsmentioning

confidence: 93%

“…This approach is similar to the one that was developed for the calculation of the layout-induced stress variation when stress was generated by means of the intentional strain engineered sources such as CESL, SMT, Si 1-x Ge x , etc. and unintentional one -STI [11].…”

Section: Simulation Of the Transistor Intrachannel Stress Componentsmentioning

confidence: 99%

“…Due to different mechanical properties of the segments in the composite layer associated with each cut-line, the boundaries between segments experience displacements. The proposed simulator generates the transistor-to-transistor stress distribution using approximate analytical solutions for different elasticity problems corresponding different stress sources [11]. This approach can be briefly explained as follows.…”

Section: Simulation Of the Transistor Intrachannel Stress Componentsmentioning

confidence: 99%

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Stress-induced Effects Caused by 3D IC TSV Packaging in Advanced Semiconductor Device Performance

Sukharev

Kteyan

Choy

et al. 2011

AIP Conference Proceedings

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Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced 3D through-silicon-via (TSV) based technologies are outlined. The paper addresses the growing need in a simulation-based design verification flow capable to analyze a design of 3D IC stacks and to determine across-die outof-spec variations in device electrical characteristics caused by the layout and through-silicon-via (TSV)/packageinduced mechanical stress. The limited characterization/measurement capabilities for 3D IC stacks and a strict "good die" requirement make this type of analysis critical for the achievement of an acceptable level of functional and parametric yield and reliability. The paper focuses on the development of a design-for-manufacturability (DFM) type of methodology for managing mechanical stresses during a sequence of designs of 3D TSV-based dies, stacks and packages. A set of physics-based compact models for a multi-scale simulation to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 3D TSV technology is proposed. A calibration technique based on fitting to measured stress components and electrical characteristics of the test-chip devices is presented. A strategy for generation of a simulation feeding data and respective materials characterization approach are proposed, with the goal to generate a database for multi-scale material parameters of wafer-level and package-level structures. For model validation, high-resolution strain measurements in Si channels of the test-chip devices are needed. At the nanoscale, the transmission electron microscopy (TEM) is the only technique available for sub-10nm strain measurements so far.

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New DfM Domain: Stress Effects

Balasinski

2013

Design for Manufacturability

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3D IC TSV-Based Technology: Stress Assessment For Chip Performance

Cited by 12 publications

References 1 publication

Nanometer deformation of elastically anisotropic materials studied by nanoindentation

Nanometer deformation of elastically anisotropic materials studied by nanoindentation

Stress-induced Effects Caused by 3D IC TSV Packaging in Advanced Semiconductor Device Performance

New DfM Domain: Stress Effects

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