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We describe a new procedure of design qualification to ensure manufacturability of deep sub-wavelength circuits. The procedure is based on optical simulation of the layout, integrated with device simulation to meet predefined conditions set forth by the layout control lines called tolerance contours. These contours, a new concept proposed in this work, are first defined for active devices based on the geometry-dependent, target MOSFET parameters, such as I ON and I OFF and for interconnecting lines, based on the resolution of the etch process, misalignment and overlap or enclosure of metal and contact layers. Drawn geometries, OPC features, or exposure conditions are then adjusted such that the simulated silicon images would fall within the tolerance contours. The concept is demonstrated on SRAM cell shrink from 120 to 100 nm technology nodes.

The cost of reticles for sub-100 nm technologies is growing twice as fast as the overall cost of new process development [1]. This makes it necessary to pursue mask cost reduction options alternative to the standard approach of one mask for one layer of one product. The several viable scenarios such as the multi-layer or multi-product (shuttle) masks can be identified by a complex technical and economical analysis, to maximize mask return on investment (ROI) over the product lifetime. The key criteria include matching of layers or products on one plate, with respect to the CD and pattern density commonality and the expected time or fab volume to the conversion to solo mask set. This work discusses the business process and the methodology of such analysis. As an example, by taking into account the cost of the exposure and the mask, one can show that for a 100 nm technology, a positive ROI would be achieved for a product or test vehicle with volume below 50 lots utilizing a multi-layer mask set. A more complete study should include considerations of design rules for blading, stepper capacity, product scheduling, yield variation over the wafer, and probability of database updates. These added restrictions limit the benefits of shared mask methodology.