Physics-Based Electromigration Models and Full-Chip Assessment for Power Grid Networks

Huang, Xin; Kteyan, Armen; Tan, Sheldon X.-D.; Sukharev, Valeriy

doi:10.1109/tcad.2016.2524540

Cited by 75 publications

(18 citation statements)

References 33 publications

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“…2.2). We remark that the three-phase EM model is more consistent with the measured wire resistance change over time than existing physics-based EM models such as [15,26,29], which do not consider the incubation time. The incubation time, which is the time between nucleation time and the time when the wire resistance changes, can be significant for the overall time-to-failure (TTF) analysis and is dependent on the wire structure as well.…”

Section: The Three-phase Physics-based Compact Em Model For Multi-segsupporting

confidence: 58%

“…In the existing physics-based EM models, the EM failure process in general can be viewed as two phases: the nucleation phase, in which the void is generated after the critical stress is reached, and the growth phase, in which the void starts to grow. Existing compact EM models are also versed in terms of the two phases, where each phase is described by timeto-failure (TTF) as a function of current density and other parameters [15,32]. However, such a simple EM model ignores the fact that when the void is nucleated or formed, it will not change the wire's resistance immediately.…”

Section: The Three-phase Physics-based Compact Em Model For Multi-segmentioning

confidence: 99%

“…Recently, a number of physics-based EM models and assessment techniques have been proposed [1,[11][12][13][14][15][16][17][18][19][20][21][22]. Huang et al proposed a compact EM time-to-failure (TTF) model based on the approximate closed form solution of Korhonen's equation for a single wire and studied the impact that wire redundancy has on EM failure in the power grid networks [12,15,23]. This work has been extended to multi-segment wires [14] and timevarying current cases [18,19].…”

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confidence: 99%

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Accelerating Electromigration Aging: Fast Failure Detection for Nanometer ICs

Sadiqbatcha

Sun

Tan

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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For practical testing and detection of electromigration (EM) induced failures in dual damascene copper interconnects, one critical issue is creating stressing conditions to induce the chip to fail exclusively under EM in a very short period of time so that EM sign-off and validation can be carried out efficiently. Existing acceleration techniques, which rely on increasing temperature and current densities beyond the known limits, also accelerate other reliability effects making it very difficult, if not impossible, to test EM in isolation. In this article, we propose novel EM wear-out acceleration techniques to address the aforementioned issue. First we show that multi-segment interconnects with reservoir and sink structures can be exploited to significantly speedup the EM wear-out process. Based on this observation, we propose three strategies to accelerate EM induced failure: reservoir-enhanced acceleration, sink-enhanced acceleration, and a hybrid method that combines both reservoir and sink structures. We then propose several configurable interconnect structures that exploit atomic reservoirs and sinks for accelerated EM testing. Such configurable interconnect structures are very flexible and can be used to achieve significant lifetime reductions iv at the cost of some routing resources. Using the proposed technique, EM testing can be carried out at nominal current densities, and at a much lower temperature compared to traditional testing methods. This is the most significant contribution of this work since, to our knowledge, this is the only method that allows EM testing to be performed in a controlled environment without the risk of invoking other reliability effects that are also accelerated by elevated temperature and current density. Simulation results show that, using the proposed method, we can reduce the EM lifetime of a chip from 10 years down to a few hours (about 10 5 X acceleration) under the 150 • C temperature limit, which is sufficient for practical EM testing of typical nanometer CMOS ICs. v Contents List of Figures vii List of Tables viii List of Tables 3.1 TTF acceleration with various sink and main-branch configurations. .. .. 3.2 TTF acceleration with various sink, main segment, and reservoir configurations 4.1 Results from temperature based accelerated technique on the structure shown in Fig.

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Section: The Three-phase Physics-based Compact Em Model For Multi-segsupporting

confidence: 58%

Section: The Three-phase Physics-based Compact Em Model For Multi-segmentioning

confidence: 99%

mentioning

confidence: 99%

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Accelerating Electromigration Aging: Fast Failure Detection for Nanometer ICs

Sadiqbatcha

Sun

Tan

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The time for void nucleation due to EM in a metal line can be expressed as a function of the stress σ T induced in that line [14]. The void nucleation time is defined as an instant in time when the stress at the cathode end of the metal line reaches critical stress (σ crit ) and expressed as:…”

Section: B Em Modelmentioning

confidence: 99%

“…where MTTF stress is the MTTF in the accelerated-stressed condition. Here, T stress is 600 K, j stress is 3 MA/cm 2 , and E a is 0.86 eV [14]. The current density in a voltage-rail segment is obtained using simulation and the MTTF of the top tier is estimated as the MTTF of the weakest link in that tier.…”

Section: B Em Modelmentioning

confidence: 99%

Reliable Power Delivery and Analysis of Power-Supply Noise During Testing in Monolithic 3D ICs

Koneru

Todri‐Sanial

Chakrabarty

2019

2019 IEEE 37th VLSI Test Symposium (VTS)

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Monolithic 3D (M3D) integration offers significant performance, power, and area benefits. However, the design of a reliable power-delivery network (PDN) is challenging for M3D ICs due to high power density and current demand per unit area. In addition, the higher susceptibility of interconnects to electromigration and stress migration increases the complexity of PDN design. We propose a framework to design a reliable PDN for M3D ICs using accurate electrical and reliability models. We leverage genetic programming to explore the design space to optimize the resources dedicated for power delivery in order to achieve reliable operation. We also analyze power-supply noise (PSN) during scan-based testing and compare it with that observed during functional operation. We quantify the impact of PSN during scan-based testing on yield loss. Our results show that the PDN design obtained using the proposed approach significantly increases the reliability of at least 40% of the wire segments in the PDN. In addition, the proposed PDN design reduces the worst-case power-supply droop by 52.5% compared to a baseline PDN. The yield loss due to power-supply droop for the proposed design is also significantly lower compared to a baseline PDN.

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