Monolithic three-dimensional (M3D) integration is gaining momentum, as it has the potential to achieve significantly higher device density compared to 3D integration based on through-silicon vias. M3D integration uses several techniques that are not used in the fabrication of conventional integrated circuits (ICs). Therefore, a detailed analysis of the M3D fabrication process is required to understand the impact of defects that are likely to occur during chip fabrication. In this article, we first analyze electrostatic coupling in M3D ICs, which arises due to the aggressive scaling of the interlayer dielectric (ILD) thickness. We then analyze defects that arise due to voids created during wafer bonding, a key step in most M3D fabrication processes. We quantify the impact of these defects on the threshold voltage of a top-layer transistor in an M3D IC. We also show that wafer-bonding defects can lead to a change in the resistance of interlayer vias (ILVs), and in some cases lead to an open in an ILV or a short between two ILVs. We then analyze the impact of these defects on path delays using HSpice simulations. We study their impact on the effectiveness of delay-test patterns for multiple instances of IWLS 2005 benchmarks in which these defects were randomly injected. Our results show that the timing characteristics of an M3D IC can be significantly altered due to coupling and wafer-bonding defects if the thickness of its ILD is less than 100nm. Therefore, for such M3D ICs, test-generation methods must be enhanced to take M3D fabrication defects into account.
Bias Temperature Instability (BTI)-induced transistor aging degrades path delay over time and may eventually induce circuit failure due to timing violations. Chip health monitoring is therefore necessary to track delay changes on a per-chip basis. We propose a method to accurately predict the fine-grained circuit-delay degradation with minimal area and performance overhead. It re-uses on-chip design-for-test (DfT) infrastructure to track the severity of run-time stress by periodiclly capturing system state and compacting it using a multiple input signature register (MISR). The captured stress information is fed to a software-based prediction model in realtime. The prediction model is trained offline using support vector regression. Aging prediction based on run-time stress monitoring can be used to proactively activate aging mitigation techniques. Experimental results for benchmark circuits highlight the accuracy of the proposed approach.
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