The semiconductor industry has followed the Moore's Law for more than 40 years. The concept of scaling based on this law is now approaching the end and to maintain the same scaling concept new routes are being investigated. These new routes are commonly identified as 'More-than-Moore' technologies and the most important of them is 3D-IC integration. By 3D-IC Integration it is possible to put more transistors on the same footprint without the need to shrink transistor sizes. However, as for any new technology, there are many challenges and issues that need to be addressed before moving to high volume manufacturing [1].In this work we present the challenges and required improvements identified for 3D stacking in case of ultra thin devices with TSVs (Thru Silicon Vias). In particular, the challenges related to wafer thinning, flip chip bumping, 3D stacking and packaging.

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Semiconductor industry, for more than four decades, has rigorously followed Moore's Law in scaling down the CMOS technologies. Although several new materials and processes are being developed to address the challenges of future technology nodes, in the coming years they will be limited with respect to functionalities that future devices will require. As a consequence a clear trend of moving from CMOS to package and system architecture can be observed. Three-dimensional (3D) technology using the well-known Through Silicon Via (TSV) interconnect is one the emerging solutions, considered today the most advanced technology, that could enable various heterogeneous integration. 3D Integration is not limited to the CMOS scaling in itself, it is rather based on bringing more functionalities by stacking different type of devices (Logic, Memory, Analog, MEMS, Passive components) while reducing the form factor of the packaging. This functional diversification is also known as More-than-Moore.

This work focuses on the analysis of recent developments and future trends of organic substrates and 2.5D interposers. In the sub 10 μm line/width space, substrate manufacturers are pushing towards traditionally foundry level Si processing dimensions. Latest R&D shows organic substrates with L/S capability down to 2/2 μm. Organic substrates and 2.5D interposers can be in many cases separated in two different groups, however certain solutions propose a combination of the two, such as embedded interposers or fine extension layers of organic substrates acting as interposers. These substrate and interposer architectural solutions are analyzed. Furthermore, organic processing options and latest feature sizes are discussed. Dielectric build up material options with low dielectric constant (Dk) and low tangent loss (Df) are analyzed and their expected thermo-mechanical property trends presented, including the coefficient of thermal expansion (CTE), Young's modulus (E) and glass transition temperature (Tg). Coreless substrates and their advantages, disadvantages, industry readiness and future development are also addressed. Furthermore, 2.5D interposer options are analyzed by type of material: Si, glass and organic. A qualitative and quantitative comparison of their features and market status is done and their future development is extrapolated. Final conclusions are made on the sub 10 μm line/width advanced substrate application space and the market interaction of organic substrates and 2.5D interposers

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