2.5D Interposers and Advanced Organic Substrates Landscape: Technology and Market Trends

Abstract

This work focuses on the analysis of recent developments and future trends of organic substrates and 2.5D interposers. In the sub 10 μm line/width space, substrate manufacturers are pushing towards traditionally foundry level Si processing dimensions. Latest R&D shows organic substrates with L/S capability down to 2/2 μm. Organic substrates and 2.5D interposers can be in many cases separated in two different groups, however certain solutions propose a combination of the two, such as embedded interposers or fine extension layers of organic substrates acting as interposers. These substrate and interposer architectural solutions are analyzed. Furthermore, organic processing options and latest feature sizes are discussed. Dielectric build up material options with low dielectric constant (Dk) and low tangent loss (Df) are analyzed and their expected thermo-mechanical property trends presented, including the coefficient of thermal expansion (CTE), Young's modulus (E) and glass transition temperature (Tg). Coreless substrates and their advantages, disadvantages, industry readiness and future development are also addressed. Furthermore, 2.5D interposer options are analyzed by type of material: Si, glass and organic. A qualitative and quantitative comparison of their features and market status is done and their future development is extrapolated. Final conclusions are made on the sub 10 μm line/width advanced substrate application space and the market interaction of organic substrates and 2.5D interposers

Improvements of the Epoxy–Copper Adhesion for Microelectronic Applications

“…The buildup layer studied was an Ajinomoto buildup film (ABF) by Ajinomoto Fine Techno., Co. (currently in use for PCB mass production ,,, and especially in smartphones assembly). This buildup sheet consists of an epoxy–phenol matrix and spherical glass fillers.…”

“…Additionally, high-frequency applications require low surface roughness. Silicon and glass interposers are relevant materials, but they are expensive . Still, a more cost-effective option relies on the improvement of organic buildup (BU) layer performances and their processing optimizations.…”

On the network design and control of an optical network: interconnecting multiple chips on a wafer

“…It is a promising solution to build larger and faster processors with high yield. With the help of the novel 2.5-D integration technology [6] [7], chips can be interposed on a wafer while an inter-chip network is fabricated on the wafer in order to accommodate the communication flows among chips. The inter-chip network is thus called Network-on-wafer(NoW) in this paper, while in some literature they are referred to as inter-chip NoC.…”