Effective negative capacitance has been postulated in ferroelectrics because there is a hysteresis in plots of polarization-electric field. Compelling experimental evidence of effective negative capacitance is presented here at room temperature in engineered devices, where it is stabilized by the presence of a paraelectric material. In future integrated circuits, the incorporation of such negative capacitance into MOSFET gate stacks would reduce the subthreshold slope, enabling low power operation and reduced self-heating.

No abstract

No abstract

A capacitance model is developed and a correction formula is derived to reconstruct the intrinsic oxide capacitance value from measured capacitance and conductance of lossy MOS devices. Due to discrepancies during processing, such as cleaning, an unwanted lossy dielectric layer is present in the oxide/semiconductor interface causing the measured capacitance in strong accumulation to be frequency dependent. The capacitance-voltage characteristics after correction are free from any frequency dispersion effect and give the actual oxide thickness in accumulation at all frequencies. Simulation of the measured capacitance-frequency curve was carried out using the model. The model was applied to SiO 2 /Si, SiO 2 /strained Si and GaO 2 /GaAs MOS capacitors.

Abstract-Performance enhancements of up to 170% in drain current, maximum transconductance, and field-effect mobility are presented for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs. A novel layer structure comprising Si/Si 0 7 Ge 0 3 on an Si 0 85 Ge 0 15 virtual substrate (VS) offers improved performance advantages and a strain-compensated structure. A high thermal budget process produces devices having excellent on/off-state drain-current characteristics, transconductance, and subthreshold characteristics. The virtual substrate does not require chemical-mechanical polishing and the same performance enhancement is achieved with and without a titanium salicide process.

Dynamic piezoresponse force microscopy: Spatially resolved probing of polarization dynamics in time and voltage domains J. Appl. Phys. 112, 052021 (2012) Co-sputtering yttrium into hafnium oxide thin films to produce ferroelectric properties Appl. Phys. Lett. 101, 082905 (2012) Safe and consistent method of spot-welding platinum thermocouple wires and foils for high temperature measurements Rev. Sci. Instrum. 83, 084901 (2012) Additional information on J. Appl. Phys.

No abstract

A method for fabricating single crystal silicon nanowires is presented using top-down optical lithography and anisotropic etching. Wire diameters as small as 10 nm are demonstrated using silicon on insulator substrates. Structural characterization confirms that wires are straight, have a triangular cross section and are without breakages over lengths of tens of microns. Electrical characterization indicates bulk like mobility values, not strongly influenced by surface scattering or quantum confinement. Processing is compatible with conventional silicon technology having much larger critical dimensions. Integrating such nanowires with a mature CMOS technology offers an inexpensive route to their exploitation as sensors. V