Impact of strained-Si thickness and Ge out-diffusion on gate oxide quality for strained-Si surface channel n-MOSFETs

Dalapati, Goutam Kumar; Chattopadhyay, Sanatan; Kwa, Kelvin S. K.; Olsen, SH; Tsang, Y.L.; Agaiby, Rimoon; O'Neill, AG; Dobrosz, P.; Bull, SJ

doi:10.1109/ted.2006.872086

Cited by 80 publications

(53 citation statements)

References 36 publications

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“…From the band alignment [15], it is obvious that strained-Si must show a smaller V t . If Ge is segregated at the interface, negative fixed charge is generated [6], which can cause a higher V t , as observed in Fig. 2.…”

Section: Resultsmentioning

confidence: 80%

“…Subthreshold swing in the strained-Si sample is also higher compared to the control-Si sample for both the prestress as well as the poststress conditions. This has also been shown to be due to the Ge out diffusion from the SiGe layer, which creates additional interface states [6]. In Fig.…”

Section: Resultsmentioning

confidence: 93%

“…The value of ∆D it is observed to be roughly in the range of mid to high 10 11 cm −2 · eV [14]. Ge diffusion to the high-κ interface has been postulated to be a cause for the degraded interface in the case of strained-Si devices [6].…”

Section: B Charge-pumping Measurementsmentioning

confidence: 98%

“…In order to enhance the inplane mobility of both electrons and holes compared to bulk, a strained-Si layer is deposited on a relaxed-Si 1−x Ge x -buffer layer [4], [5]. However, in the case of strained-Si on Si 1−x Ge x , Ge diffusion to the Si/ HfO 2 interface may result in an increase in the interface state and fixed-charge densities for these devices [6]. Furthermore, the presence of border traps [7], which can exchange charge with Si on a time-scale ∼1 s, can increase 1/f noise as reported in the study in [8].…”

Section: Introductionmentioning

confidence: 99%

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Border-Trap Characterization in High-$\kappa$ Strained-Si MOSFETs

Maji

Duttagupta

Rao

et al. 2007

IEEE Electron Device Lett.

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Abstract-In this letter, we focus on the border-trap characterization of TaN/HfO 2 /Si and TaN/HfO 2 /strained-Si/Si 0.8 Ge 0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 nm. Drain-current hysteresis method is used to characterize the border traps, and it is found that border traps are higher in the case of high-κ films on strainedSi/Si 0.8 Ge 0.2 . These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of high-κ films on strained-Si are also proposed.

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Section: Resultsmentioning

confidence: 80%

Section: Resultsmentioning

confidence: 93%

Section: B Charge-pumping Measurementsmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

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Border-Trap Characterization in High-$\kappa$ Strained-Si MOSFETs

Maji

Duttagupta

Rao

et al. 2007

IEEE Electron Device Lett.

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“…The simulated structure has a s-Si layer of 10 nm thickness and an oxide layer thickness of (a) 10 nm and (b) 4 nm. A characteristic hump exists in the C-V curves as the gate voltage is swept from flat band to accumulation, due to the hole confinement phenomenon induced by the bandgap discontinuity [8,9] where holes are confined at the strained Si/SiGe heterointerface which acts as a potential barrier. This effect is stronger when increasing the germanium concentration.…”

Section: Methodsmentioning

confidence: 99%

Simulation of the electrical characteristics of MOS capacitors on strained‐silicon substrates

Kelaidis

Skarlatos

Tsamis

2008

Phys. Status Solidi (c)

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In this work, we analyze the electrical characteristics of MOS capacitors fabricated on strained silicon substrates using the commercial software Taurus/Synopsis. The effect of various parameters such as Germanium concentration in the Si1–xGex virtual substrate, thickness of the strained‐Silicon layer, oxide thickness, fixed charge and interface trapped charge on capacitance – voltage characteristics is examined. Experimental data are compared with simulation results. A strong influence of the s‐Si/SiGe heterostructure and its proximity to the s‐Si/SiO2 on the electrical characteristics of the system exists. Oxide charge inserted into simulation in order to fit experimental data shows an increase of charge with decreasing s‐Si thickness. The effect of interface traps on simulated C‐V characteristics is identical when traps are situated in the s‐Si/SiO2 or the s‐Si/SiGe interface. When increasing the thermal budget by increasing the post oxidation annealing time, the decrease of the hump phenomenon on the C‐V curves can be attributed to the Germanium diffusion, according to simulation. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

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Strain Engineering in Modern Field Effect Transistors

Sinha¹

2021

Electrical and Electronic Devices, Circuits, and Materials

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Impact of strained-Si thickness and Ge out-diffusion on gate oxide quality for strained-Si surface channel n-MOSFETs

Cited by 80 publications

References 36 publications

Border-Trap Characterization in High-$\kappa$ Strained-Si MOSFETs

Border-Trap Characterization in High-$\kappa$ Strained-Si MOSFETs

Simulation of the electrical characteristics of MOS capacitors on strained‐silicon substrates

Strain Engineering in Modern Field Effect Transistors

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