2014
DOI: 10.1021/nl5017255
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Experimental Observation of Negative Capacitance in Ferroelectrics at Room Temperature

Abstract: Effective negative capacitance has been postulated in ferroelectrics because there is a hysteresis in plots of polarization-electric field. Compelling experimental evidence of effective negative capacitance is presented here at room temperature in engineered devices, where it is stabilized by the presence of a paraelectric material. In future integrated circuits, the incorporation of such negative capacitance into MOSFET gate stacks would reduce the subthreshold slope, enabling low power operation and reduced … Show more

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Cited by 220 publications
(121 citation statements)
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“…In the presence of the intermediate metal electrode between the ferroelectric and the dielectric capacitor, the dielectric capacitor does not result in a depolarizing field in the ferroelectric at V S ¼ 0-this is unlike the cases in ferroelectric-dielectric heterostructures without intermediate metallic layers. 7,8,11,12,15 As such, the ferroelectric can be polarized even at V S ¼ 0. 22 For the homogeneous switching simulations (details in Sec.…”
mentioning
confidence: 99%
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“…In the presence of the intermediate metal electrode between the ferroelectric and the dielectric capacitor, the dielectric capacitor does not result in a depolarizing field in the ferroelectric at V S ¼ 0-this is unlike the cases in ferroelectric-dielectric heterostructures without intermediate metallic layers. 7,8,11,12,15 As such, the ferroelectric can be polarized even at V S ¼ 0. 22 For the homogeneous switching simulations (details in Sec.…”
mentioning
confidence: 99%
“…The fact that the ferroelectric material can exhibit such a state of negative capacitance has already been demonstrated. 3,4,[6][7][8][9][10][11][12][13][14][15][16][17][18] Therefore, if another dielectric capacitor is placed in series with the ferroelectric [as shown schematically in Fig. 1(b)], a voltage amplification is expected across the dielectric capacitor.…”
mentioning
confidence: 99%
“…The NC concept is obviously very attractive because it could enable low-voltage/low-power operation in field effect transistors [50][51][52]. Experimental work on Pb(Zr 0.2 Ti 0.8 )O 3 /SrTiO 3 (STO) [51], Ba 0.8 Sr 0.2 TiO 3 /LaAlO 3 (LAO) [52], and BaTiO 3 (BTO)/STO [53] shows that the capacitance of the constituent FE layer could be negative because the composite capacitance is larger than the capacitance of the STO or LAO layer. We note that NC and a negative dielectric constant from the FE layer can indeed be obtained if the CIS methodology is applied to a FE/DE or FE/PE bilayer or superlattice.…”
Section: Discussionmentioning
confidence: 99%
“…The key to hysteresis-free FeFET design, which is required for analog and digital applications, is capacitance matching: positive capacitance of intrinsic MOSFET below the ferroelectric should stabilize its negative capacitance. To our knowledge, so far the non-hysteretic electrical characteristics can be experimentally observed in ferroelectric-dielectric bilayer [5,6]. Integration of well-known perovskite-type ferroelectrics on intrinsic MOSFET is very challenging due to issues like low-quality interface, mismatch of thermal expansion coefficients between ferroelectric oxide and Si, and incomplete screening, which have not been addressed [7].…”
Section: Introductionmentioning
confidence: 99%