High-performance nMOSFETs using a novel strained Si/SiGe CMOS architecture

Olsen, SH; O'Neill, AG; Driscoll, L.S.; Kwa, Kelvin S. K.; Chattopadhyay, Sanatan; Waite, A.M.; Tang, Y.T.; Evans, A G R; Norris, David J.; Cullis, A. G.; Paul, Douglas J.; Robbins, David J.

doi:10.1109/ted.2003.815603

Cited by 86 publications

(41 citation statements)

References 33 publications

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“…For the other data plotted on this figure, the technological processes for NMOS fabrication including a GBL were similar and lead to close mobility values [11,45,47]. Our results obtained from Monte Carlo simulation are in accordance with the best experimental mobility enhancements [7,12,13]. …”

Section: Effect Of Strain On Electron Mobilitysupporting

confidence: 81%

“…6 shows a discrepancy between the various experimental results. For instance, for x = 0.30, the electron mobility can be enhanced by ≈ 80% [11] or by 120% [12,13]. These differences can be explained in terms of surface roughness of the strained Si/Si 1-x Ge x .…”

Section: Effect Of Strain On Electron Mobilitymentioning

confidence: 99%

“…Now efforts are made to transfer this advantage in CMOS technology on either bulk or insulating substrate [7][8][9][10]. It has been demonstrated that the effective electron mobility in MOS structures can be substantially enhanced using tensile strained-Si channel grown on SiGe buffer layer [7,11,12,13].…”

Section: Introductionmentioning

confidence: 99%

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Electron effective mobility in strained-Si/Si1−xGex MOS devices using Monte Carlo simulation

Aubry-Fortuna

Dollfus

Galdin‐Retailleau

2005

Solid-State Electronics

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Based on Monte Carlo simulation, we report the study of the inversion layer mobility in n-channel strained Si/ Si 1-x Ge x MOS structures. The influence of the strain in the Si layer and of the doping level is studied. Universal mobility curves µ eff as a function of the effective vertical field E eff are obtained for various state of strain, as well as a fall-off of the mobility in weak inversion regime, which reproduces correctly the experimental trends. We also observe a mobility enhancement up to 120 % for strained Si/ Si 0.70 Ge 0.30 , in accordance with best experimental data. The effect of the strained Si channel thickness is also investigated: when decreasing the thickness, a mobility degradation is observed under low effective field only.

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Section: Effect Of Strain On Electron Mobilitysupporting

confidence: 81%

Section: Effect Of Strain On Electron Mobilitymentioning

confidence: 99%

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Electron effective mobility in strained-Si/Si1−xGex MOS devices using Monte Carlo simulation

Aubry-Fortuna

Dollfus

Galdin‐Retailleau

2005

Solid-State Electronics

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“…Up to 170% performance enhancements in drain current, maximum transconductance, and field-effect mobility have been reported for the conventional strained-Si MOSFET, which includes a tensile-strained Si channel on a thick Si x Ge 1-x relaxed buffer [5].…”

Section: Strained-sige Complementary Mosfets Adopting Different Thickmentioning

confidence: 99%

Strained-SiGe Complementary MOSFETs Adopting Different Thickness of Silicon Cap Layers for Low Power and High Performance Applications

Mheen¹,

Song²,

Kang³

et al. 2005

ETRI J

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, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high-electron-mobility Si surface channel in nMOSFETs and a compressively strained high-hole-mobility Si 0.8 Ge 0.2 buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate-leakage levels. Unlike the conventional strained-Si CMOS employing a relatively thick (typically > 2 µm) Si x Ge 1-x relaxed buffer layer, the strained-SiGe CMOS with a very thin (20 nm) Si 0.8 Ge 0.2 layer in this study showed a negligible self-heating problem. Consequently, the proposed strained-SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.

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“…For long time, strain material has been known to improve the channel transport properties of complementary MOS (CMOS) devices [8]. CMOS devices with strained channel are actively discussed and analyzed from simulation and experimental point of views [9,10] followed by the incorporation of strained silicon into the most recent silicon device technology by leading IC industries [11]. The strained silicon may be the noble alternative to the silicon technology due to the improved transport characteristics.…”

Section: Introductionmentioning

confidence: 99%

Quantum electron transport modeling in uniaxially strained silicon channel of double‐gate MOSFETs

Fitriawan

Ogawa

Souma

et al. 2008

Phys. Status Solidi (c)

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This paper reports the calculation of quantum electron transport in double‐gate metal oxide semiconductor field effects transistors (MOSFETs) with uniaxially strained silicon channel. The calculation is formulated based on multiband non‐equilibrium Green's function (NEGF) method coupled self‐consistently with the Poisson equation. The empirical sp3s * tight binding approximation (TBA) model with nearest neighbor coupling is employed to obtain more realistic band structure in the formulation. We compare the carrier transport characteristics of simulated MOSFETs with strained channel to those of without strain. The simulation results show that the presence of uniaxially strain induce the current enhancement in the devices. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

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High-performance nMOSFETs using a novel strained Si/SiGe CMOS architecture

Cited by 86 publications

References 33 publications

Electron effective mobility in strained-Si/Si1−xGex MOS devices using Monte Carlo simulation

Electron effective mobility in strained-Si/Si1−xGex MOS devices using Monte Carlo simulation

Strained-SiGe Complementary MOSFETs Adopting Different Thickness of Silicon Cap Layers for Low Power and High Performance Applications

Quantum electron transport modeling in uniaxially strained silicon channel of double‐gate MOSFETs

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