A capacitance model is developed and a correction formula is derived to reconstruct the intrinsic oxide capacitance value from measured capacitance and conductance of lossy MOS devices. Due to discrepancies during processing, such as cleaning, an unwanted lossy dielectric layer is present in the oxide/semiconductor interface causing the measured capacitance in strong accumulation to be frequency dependent. The capacitance-voltage characteristics after correction are free from any frequency dispersion effect and give the actual oxide thickness in accumulation at all frequencies. Simulation of the measured capacitance-frequency curve was carried out using the model. The model was applied to SiO 2 /Si, SiO 2 /strained Si and GaO 2 /GaAs MOS capacitors.

Abstract-Performance enhancements of up to 170% in drain current, maximum transconductance, and field-effect mobility are presented for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs. A novel layer structure comprising Si/Si 0 7 Ge 0 3 on an Si 0 85 Ge 0 15 virtual substrate (VS) offers improved performance advantages and a strain-compensated structure. A high thermal budget process produces devices having excellent on/off-state drain-current characteristics, transconductance, and subthreshold characteristics. The virtual substrate does not require chemical-mechanical polishing and the same performance enhancement is achieved with and without a titanium salicide process.

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Articles you may be interested inEvaluation of interface state density of strained-Si metal-oxide-semiconductor interfaces by conductance method Electron mobility enhancement in strained-germanium n -channel metal-oxide-semiconductor field-effect transistors Appl. Phys. Lett. 91, 102103 (2007); 10.1063/1.2779845 Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors J. Appl. Phys. 97, 011101 (2005); 10.1063/1.1819976Strained Si/strained Ge dual-channel heterostructures on relaxed Si 0.5 Ge 0.5 for symmetric mobility p-type and n-type metal-oxide-semiconductor field-effect transistors Channel conductance has been employed to extract several important parameters such as threshold voltage, gain, effective channel length, series resistance, and mobility for strained-Si metal-oxide-semiconductor field-effect-transistors fabricated on relaxed silicon-germanium virtual substrates with Ge composition up to 25%. Analytical models have been developed by taking into account the effect of strain ͑i.e., Ge composition͒ on these parameters. The low field mobility of the devices has been found to increase linearly up to a Ge composition of 25% in the virtual substrate. A modified channel conductance technique has been used to extract critical fields accurately. This has also been used to predict the dependence of mobility on electric field in a strained-Si device. The critical field for silicon devices has been found to be 65 kV cm −1 , while for strained-Si devices, it has been found to decrease from 62.5 to 30 kV cm −1 with increasing Ge composition ͑15% to 25%͒ in the virtual substrate. The reported results are useful for the design and simulation of strained-Si devices.

The enhanced electrical performance of dual quantum well strained Si/SiGe n-channel MOSFETs has been investigated as a function of SiGe material quality. The higher electron mobility in strained Si compared with bulk Si has been translated into performance gains in terms of device transconductance and on-state drain current exceeding 120% compared with simultaneously fabricated Si controls. Increased performance was demonstrated for a wide range of gate lengths and operating conditions. Trade-offs between optimum device design and SiGe material quality have been investigated. The greatest performance enhancements are achieved through device fabrication on SiGe virtual substrate material grown by low-pressure chemical vapour deposition (LPCVD) at high temperature. Improved surface morphology, defect density and gate oxide quality are found to be the dominating factors in the enhanced performance of the devices compared with strained Si/SiGe MOSFETs fabricated on LPCVD material grown at low temperature. However, even degraded SiGe material arising from low temperature LPCVD growth resulted in strained Si/SiGe n-channel MOSFETs exhibiting significant improvements in device operation compared with conventional Si MOSFETs. The performance advantages offered by strained Si/SiGe devices fabricated on material grown at both low and high temperatures exceed that of a typical Si CMOS technology generation.

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Articles you may be interested inSuper critical thickness SiGe-channel heterostructure p -type metal-oxide-semiconductor field-effect transistors using laser spike annealing Improved gate oxide integrity of strained Si n -channel metal oxide silicon field effect transistors using thin virtual substrates J. Appl. Phys. 103, 094508 (2008); 10.1063/1.2917286 Effect of Si cap layer on parasitic channel operation in Si/SiGe metal-oxide-semiconductor structures J. Appl. Phys. 93, 3545 (2003); 10.1063/1.1542916Hole mobility enhancements and alloy scattering-limited mobility in tensile strained Si/SiGe surface channel metal-oxide-semiconductor field-effect transistors