Evaluation of strained Si/SiGe material for high performance CMOS

Abstract

The enhanced electrical performance of dual quantum well strained Si/SiGe n-channel MOSFETs has been investigated as a function of SiGe material quality. The higher electron mobility in strained Si compared with bulk Si has been translated into performance gains in terms of device transconductance and on-state drain current exceeding 120% compared with simultaneously fabricated Si controls. Increased performance was demonstrated for a wide range of gate lengths and operating conditions. Trade-offs between optimum device design and SiGe material quality have been investigated. The greatest performance enhancements are achieved through device fabrication on SiGe virtual substrate material grown by low-pressure chemical vapour deposition (LPCVD) at high temperature. Improved surface morphology, defect density and gate oxide quality are found to be the dominating factors in the enhanced performance of the devices compared with strained Si/SiGe MOSFETs fabricated on LPCVD material grown at low temperature. However, even degraded SiGe material arising from low temperature LPCVD growth resulted in strained Si/SiGe n-channel MOSFETs exhibiting significant improvements in device operation compared with conventional Si MOSFETs. The performance advantages offered by strained Si/SiGe devices fabricated on material grown at both low and high temperatures exceed that of a typical Si CMOS technology generation.

Gate leakage mechanisms in strained Si devices

“…Strained Si n-MOSFETs were fabricated on relaxed SiGe virtual substrates using a conventional process described previously. 12 The virtual substrates were grown by low-pressure chemical vapor deposition. Devices had 6 nm thermally grown gate oxides, determined by capacitancevoltage measurements.…”

“…Another challenge for globally strained Si/ SiGe MOSFETs is material quality, since epitaxial growth of strained layers on relaxed virtual substrates leads to surface roughness, 10,11 which can impact photolithography in addition to gate oxide quality. 12 High quality gate dielectrics are paramount if MOSFETs with high performance and good reliability are to be realized. Ge outdiffusion from a SiGe virtual substrate or a SiGe source/drain stressor during high thermal budget processing can degrade gate oxide interface quality.…”

Electron effective mobility in strained-Si/Si1−xGex MOS devices using Monte Carlo simulation

“…In the case of electrons this effect has been clearly shown from mobility measurement and calculation in SiGe-Si-SiGe quantum wells [2][3][4] and it has been used for designing high-performance MODFET with low noise figure and high cut-off and maximum oscillation frequencies [5][6]. Now efforts are made to transfer this advantage in CMOS technology on either bulk or insulating substrate [7][8][9][10]. It has been demonstrated that the effective electron mobility in MOS structures can be substantially enhanced using tensile strained-Si channel grown on SiGe buffer layer [7,11,12,13].…”

Structural characterization of strained silicon grown on a SiGe buffer layer

“…A compositionally graded layer to confine threading dislocations was grown by gradually accommodating the lattice mismatch between Si 1−x Ge x layers [12,13] on (1 0 0) silicon substrate via molecular beam epitaxy (MBE) in which the growth condition was shown in [14,15]. A 630 nm thick layer of the fully relaxed Si 0.7 Ge 0.3 was grown on top of the graded layer, followed by a 50 nm strained Si-capping layer.…”

“…In contrast to the misfit dislocations, the threading dislocations primarily arise from the dislocated substrate/buffer layer and dislocation loops nucleated from the step edgy [11]. Therefore, the threading dislocation density can be reduced by alternative growth methods, such as an introduction of a graded buffer layer used in our study [12,13]. These misfit/threading dislocations are primarily observed using transmission electron microscopy (TEM), which, unfortunately, has disadvantages such as complex and destructive sample preparation and it is time consuming.…”