Design, fabrication and characterisation of strained Si∕SiGe MOS transistors

Olsen, SH; Kwa, Kelvin S. K.; Driscoll, L.S.; Chattopadhyay, Sanatan; O'Neill, AG

doi:10.1049/ip-cds:20040995

Cited by 25 publications

(9 citation statements)

References 35 publications

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“…The peak hole mobility for strained-Si device is 140cm 2 /Vs, 50% enhancement compared with that of bulk Si. The device performance of the strained-Si p-MOSFET is roughly equal to that in the most previous reports [1,9] , but did not reach the predicted values. Further research are needed to increase Ge composition and strain in the strained-Si layer, and reduce defects.…”

Section: Resultssupporting

confidence: 72%

“…This is because the strained-Si has higher electron and hole mobility than conventional Si [1] . A recently published report of effective hole mobility was 30% higher than that of conventional Si [2] .…”

Section: Introductionmentioning

confidence: 95%

“…But the thick SiGe virtual substrates by UHVCVD growth still suffer from a low thermal conductivity and surface fluctuation with amplitude in a range of 15~20nm. The self-heating of the strained-Si devices arises from the lower thermal 1 [5] and results in a significantly elevated channel temperature [6] . Some attempts have been reported, such as, growth of defect-rich layers at low temperature [7] .…”

Section: Introductionmentioning

confidence: 99%

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Fabrication of strained-Si channel p-MOSFET’s on ultra-thin SiGe virtual substrates

Mo-hua

Tan

et al. 2006

J. of Electron.(China)

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In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor (p-MOSFET) is presented. Built on strained-Si/240nm relaxed-Si 0.8 Ge 0.2 / 100nm Low Temperature Si (LT-Si)/10nm Si buffer was grown by Molecular Beam Epitaxy (MBE), in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed. Measurement indicates that the strained-Si p-MOSFET's (L=4.2μm) transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si. The maximum hole mobility for strained-Si device is 140cm 2 /Vs. The device performance is comparable to devices achieved on several μm thick composition graded buffers and relaxed-SiGe layer virtual substrates.

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Section: Resultssupporting

confidence: 72%

Section: Introductionmentioning

confidence: 95%

Section: Introductionmentioning

confidence: 99%

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Fabrication of strained-Si channel p-MOSFET’s on ultra-thin SiGe virtual substrates

Mo-hua

Tan

et al. 2006

J. of Electron.(China)

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“…12 Another related observation is that dynamic threshold (DT) MOSFETs, where the bulk terminal is connected to the gate B V = G V , can present higher transconductance and significantly reduced 1/ / noise than that when the device is operated in the f conventional mode with the bulk grounded. [88][89][90] Deen and Marinov found a reduction in the 1/f / noise magnitude by 8 dB/V when a forward bias was applied on the bulk of a Si pMOSFET. 14 In the authors' work, a corresponding reduction around 5 dB/V has been observed in Si pMOSFETs with high-k gate dielectrics.…”

Section: Impact Of Substrate Voltagementioning

confidence: 99%

Low-Frequency Noise In Advanced Mos Devices

2007

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“…However, the greatest success in the area of real transistor devices promoting in millimeter waves, is obtained mainly in strained planar heterostructures containing quantum layers of the Si 1-х Ge х solid solution with electron or hole conductance [1][2][3]. Much less works are devoted to studying the properties of relaxed heterostructures with an electron transport channel in the silicon layers.…”

Section: Introductionmentioning

confidence: 99%

Features of electronic transport in relaxed Si/Si1−XGeX heterostructures with high doping level

Orlov

nikova

Orlov

et al. 2013

Physica E: Low-dimensional Systems and Nanostructures

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The low-temperature electrical and magnetotransport characteristics of partially relaxed Si/Si 1-x Ge x heterostructures with two-dimensional electron channel (n e ≥ 10 12 cm -2 ) in an elastically strained silicon layer of nanometer thickness have been studied. The detailed calculation of the potential and of the electrons distribution in layers of the structure was carried out to understand the observed phenomena.The dependence of the tunneling transparency of the barrier separating the 2D and 3D transport channels in the structure, was studied as a function of the doping level, the degree of blurring boundaries, layer thickness, degree of relaxation of elastic stresses in the layers of the structure. Tunnel characteristics of the barrier between the layers were manifested by the appearance of a tunneling component in the current-voltage characteristics of real structures. Instabilities, manifested during the magnetotransport measurements using both weak and strong magnetic fields are explained by the transitions of charge carriers from the two-dimensional into three-dimensional state, due to interlayer tunneling transitions of electrons.

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Design, fabrication and characterisation of strained Si∕SiGe MOS transistors

Cited by 25 publications

References 35 publications

Fabrication of strained-Si channel p-MOSFET’s on ultra-thin SiGe virtual substrates

Fabrication of strained-Si channel p-MOSFET’s on ultra-thin SiGe virtual substrates

Low-Frequency Noise In Advanced Mos Devices

Features of electronic transport in relaxed Si/Si1−XGeX heterostructures with high doping level

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