Study of Single- and Dual-Channel Designs for High-Performance Strained-Si–SiGe n-MOSFETs

Olsen, SH; O'Neill, AG; Chattopadhyay, Sanatan; Driscoll, L.S.; Kwa, Kelvin S. K.; Norris, David J.; Cullis, A. G.; Paul, Douglas J.

doi:10.1109/ted.2004.830652

Cited by 34 publications

(12 citation statements)

References 28 publications

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“…1). SiGe layer can enhance the electron mobility and the mobilities in strained layer is depend on the transport direction, which is perpendicular or parallel to the original SiGe growth [21]. The electron mobility increased in the out of plane direction and decreased during in plane direction due to the splitting of the valleys into lower four -fold and higher two fold states (Fig.7) in conduction band [26].…”

Section: Device Performance and Analysismentioning

confidence: 99%

Single and dual strained channel analysis of vertical strained — SiGe impact ionization MOSFET (VESIMOS)

Saad

Seng

Zuhir

et al. 2013

RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics

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Single Channel (SC) and Dual Channel (DC) VerticalStrained-SiGe Impact Ionization MOSFET (VESIMOS) has been successfully simulated and analyzed in this paper. Found out that SC VESIMOS operate in conventional MOSFET mode at V DS = 1.75V, with 10% to 30% Ge mole fraction. However for Ge=50%, it's operated in Impact Ionization (II) mode with fast switching speed of subthreshold value, S=9.8 mV/dec. A better performance in threshold voltage, V TH , S value and I ON /I OFF ratio were found in DC VESIMOS as compared to SC VESIMOS. The V TH =0.6V, S=10.98 mV/dec and I ON /I OFF = 1×10 13 were measured in DC VESIMOS with Ge=30% that clarify the advantage of DC utilization on VESIMOS device. These improvements were mainly due to the enhancement of electron mobility from 600 m 2 /V-s (first channel) to 1400 m 2 /V-s (second channel). The electron mobility was increased due to the splitting of conduction band valley into six fold where the electron mass are reduced in out of plane direction and thus enhanced the mobility of electron.

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Section: Device Performance and Analysismentioning

confidence: 99%

Single and dual strained channel analysis of vertical strained — SiGe impact ionization MOSFET (VESIMOS)

Saad

Seng

Zuhir

et al. 2013

RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics

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“…Strained silicon (Si) technology has been identified as source of performance enhancement in complementary metal oxide on semiconductor (CMOS) technology [1].…”

Section: Abstract-the Impact Of Self Heating In Strained Simentioning

confidence: 99%

Improved Analog Performance in Strained-Si MOSFETs Using the Thickness of the Silicon–Germanium Strain-Relaxed Buffer as a Design Parameter

Alatise

Kwa

Olsen

et al. 2009

IEEE Trans. Electron Devices

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“…For shallow source/drain, doping needs to be increased to keep the sheet resistance constant otherwise, increased series resistance would be encountered, which induces difficulty in accessing the channel, hence vitiates the device performance radically . Therefore, the concept of strain engineering to develop new heterostructure devices have been explored to some extent and has become a crucial feature in present CMOS technology since it enhances the drain current without further gate length scaling, which seemed to be a promising solution for further improvement in device performances …”

Section: Introductionmentioning

confidence: 99%

Development of Tri‐Layered s‐Si/s‐SiGe/s‐Si Channel Heterostructure‐on‐Insulator MOSFET for Enhanced Drive Current

Khiangte

Dhar

2018

Physica Status Solidi (b)

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Incubation of strain technology in the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) arena by developing heterostructure layers combined of Si and SiGe layers within the channel is employed widely. Development of a fully depleted novel device featuring a distinguished trilayer heterostructure channel consisting of mobility enriched double strained Si (s-Si) layers sandwiching strained SiGe (s-SiGe) in between has been the crux of this paper. The channel with s-Si/s-SiGe/s-Si significantly enhances electron mobility in comparison to conventional device of s-Si on relaxed SiGe channel, leading to improved device performance without implementing additional scaling. The tri-layered channel and the conventional device are compared and eloquent drain current enhancement of 49% attained with minimal value of threshold voltage roll-off with increased strain infusion within the channel region, which augments electron mobility in the s-Si layers. Augmented maximum transconductance for sub-50 nm channel length due to velocity overshoot enhancement of 119% in comparison to conventional device acquired lead to %25% decrease in threshold voltage by band structure lowering with the instigation of the strain technology in the short channel device attained. Hence, with higher carrier mobility and improved drive current double strained Si heterostructure on insulator (HOI) MOSFET device is designed and developed.

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Study of Single- and Dual-Channel Designs for High-Performance Strained-Si–SiGe n-MOSFETs

Cited by 34 publications

References 28 publications

Single and dual strained channel analysis of vertical strained — SiGe impact ionization MOSFET (VESIMOS)

Single and dual strained channel analysis of vertical strained — SiGe impact ionization MOSFET (VESIMOS)

Improved Analog Performance in Strained-Si MOSFETs Using the Thickness of the Silicon–Germanium Strain-Relaxed Buffer as a Design Parameter

Development of Tri‐Layered s‐Si/s‐SiGe/s‐Si Channel Heterostructure‐on‐Insulator MOSFET for Enhanced Drive Current

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Study of Single- and Dual-Channel Designs for High-Performance Strained-Si–SiGe n-MOSFETs

Cited by 34 publications

References 28 publications

Single and dual strained channel analysis of vertical strained &#x2014; SiGe impact ionization MOSFET (VESIMOS)

Single and dual strained channel analysis of vertical strained &#x2014; SiGe impact ionization MOSFET (VESIMOS)

Improved Analog Performance in Strained-Si MOSFETs Using the Thickness of the Silicon&#x2013;Germanium Strain-Relaxed Buffer as a Design Parameter

Development of Tri‐Layered s‐Si/s‐SiGe/s‐Si Channel Heterostructure‐on‐Insulator MOSFET for Enhanced Drive Current

Contact Info

Product

Resources

About

Single and dual strained channel analysis of vertical strained — SiGe impact ionization MOSFET (VESIMOS)

Single and dual strained channel analysis of vertical strained — SiGe impact ionization MOSFET (VESIMOS)

Improved Analog Performance in Strained-Si MOSFETs Using the Thickness of the Silicon–Germanium Strain-Relaxed Buffer as a Design Parameter