Abstract-This letter presents an electrical method to reduce dark current as well as increase well capacity of four-transistor pixels in a CMOS image sensor, utilizing a small negative offset voltage to the gate of the transfer (TX) transistor particularly only when the TX transistor is off. As a result, using a commercial pixel in a 0.18 µm CMOS process, the voltage drop due to dark current of the pinned photodiode (PPD) is reduced by 6.1 dB and the well capacity is enhanced by 4.4 dB, which is attributed to the accumulated holes and the increased potential barrier near the PPD, respectively.Index Terms-CMOS image sensor (CIS), dark current, fourtransistor pixel, hole accumulation diode, imager, pinned photodiode (PPD), well capacity.

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, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high-electron-mobility Si surface channel in nMOSFETs and a compressively strained high-hole-mobility Si 0.8 Ge 0.2 buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate-leakage levels. Unlike the conventional strained-Si CMOS employing a relatively thick (typically > 2 µm) Si x Ge 1-x relaxed buffer layer, the strained-SiGe CMOS with a very thin (20 nm) Si 0.8 Ge 0.2 layer in this study showed a negligible self-heating problem. Consequently, the proposed strained-SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.

A new simple method to obtain real-time high-resolution three-dimensional (3D) images based on a static unitary detector (STUD) is reported. The STUD consists of a common bias network, a partitioned photodetector, a preamplifier array and a combiner, which makes it possible to easily increase the effective photo-detection area for a wider 3D image acquisition without affecting the ability to detect short laser pulses for high-resolution 3D images. From an implemented experimental prototype based on a STUD, the intensity and 3D images with a very high resolution (320 pixels × 240 pixels) were obtained. The achieved range resolution and the spatial resolution of remote 3D objects at 50 m were measured to be <0.3 and 1.1 cm, respectively.

By utilizing a remote ultraviolet ozone source, a low-temperature (600-700 • C) radical-assisted oxidation (RAO) process to produce high-quality ultrathin (1.4-3.7 nm) gate oxides was successfully developed for the fabrication of high-performance SiGe/Si metal-oxide-semiconductor field effect transistors (MOSFETs). The oxide grown by this technique showed much improved leakage and breakdown properties, compared with that grown without ozone. The reactive oxygen species in the RAO process seemed to cure the unpaired bonds in oxide networks making them more robust and dense, without an increase in thermal budget. The Si 0.8 Ge 0.2 p-channel MOSFET with a RAO gate oxide exhibited superior device and 1/f noise characteristics to that with a standard higher temperature furnace oxide. This was because of the suppressed Ge-related gate-oxide degradation at the reduced process temperature when the Si-cap layer was thinned to below 2 nm. These suggest that the RAO process is particularly suitable for SiGe/Si MOSFET devices requiring a high-quality and low-temperature oxidation process.

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