Analysis on the effect of parallel current path on the quality factor of CMOS spiral inductors for 1–10 GHz

Suh, Dongwoo; Mheen, Bongki

doi:10.1016/j.mee.2004.11.014

Cited by 6 publications

(3 citation statements)

References 7 publications

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“…Most notably, this has been achieved using designs such as multilayered, stacked inductors (MLSIs), see Figure 1, which increase the inductance value due to the mutual magnetic coupling [1], and multiple shunt inductors, which lower the resistance [2,3]. For those researchers concerned with cost, much of the focus is within analyzing the process with respect to the standard complementary metal oxide semiconductor (CMOS) technology, where the key factors in determining the cost are (1) feature size, (2) number and kinds of layers, and (3) chip area occupied [4]. Within this work, we focus on simplifying the fabrication of integrated inductors for the emerging area of power converter technology.…”

Section: Introductionmentioning

confidence: 99%

Multilayer, Stacked Spiral Copper Inductors on Silicon with Micro-Henry Inductance Using Single-Level Lithography

Reissman

Park

Garcia

2012

Active and Passive Electronic Components

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We present copper structures composed of multilayer, stacked inductors (MLSIs) with tens of micro-Henry inductance for use in low frequency (sub 100 MHz), power converter technology. Unique to this work is the introduction of single-level lithography over the traditional two-level approach to create each inductor layer. The result is a simplified fabrication process which results in a reduction in the number of lithography steps per inductor (metal) layer and a reduction in the necessary alignment precision. Additionally, we show that this fabrication process yields strong adhesion amongst the layers, since even after a postprocess abrasion technique at the inner diameter of the inductors, no shearing occurs and connectivity is preserved. In total, three separate structures were fabricated using the single-level lithography approach, each with a three-layered, stacked inductor design but with varied geometries. Measured values for each of the structures were extracted, and the following results were obtained: inductance values of 24.74, 17.25, and 24.74 μH, self-resonances of 9.87, 5.72, and 10.58 MHz, and peak quality factors of 2.26, 2.05, and 4.6, respectively. These values are in good agreement with the lumped parameter model presented.

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Section: Introductionmentioning

confidence: 99%

Multilayer, Stacked Spiral Copper Inductors on Silicon with Micro-Henry Inductance Using Single-Level Lithography

Reissman

Park

Garcia

2012

Active and Passive Electronic Components

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“…In the recent years, a large amount of modeling, characterization, and design work has been done to study air-core spiral inductors on silicon technology for both radio-frequency integrated circuits (RFICs) and monolithic microwave integrated circuits (MMICs). In order to improve the quality (Q) factor of the spiral inductors, many researches focus on the multi-layer structure, such as series stacked structure increasing the inductance value due to the mutual magnetic coupling [2], and double or multiple shunt structure dropping the series resistance [3,4]. However, for the spiral inductors used in fully integrated DC-DC converter, the simply series or shunt connection multilayer structure fabricated in conventional CMOS silicon process is difficult to satisfy the desired Q value, current capability and the limited of the occupied area directly [5].…”

Section: Introductionmentioning

confidence: 99%

A Fully-Integrated Buck Converter Design and Implementation for On-Chip Power Supplies

Li¹

2012

JCP

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A 5V-2.5V fully-integrated low-power buck converter was designed and implemented using 0.5µm CMOS technology. The critical circuits of the high frequency controller and an on-chip multi-layer spiral inductor were presented. The structure of multi-layer spiral inductor having parallel and series branches of the metal strip. As the result that the parallel branching structure greatly reduced the series resistance and the series branching structure greatly improved the series inductance of the inductor, the structure can achieve quality factor and current capability enhancement while compatible with conventional CMOS process. The quality factor was quantitatively analyzed with a scalable model and its origin was investigated at a structural point of view. From chip measurement results, when the converter is running at the rated load, the average output voltage of 2.5V, the output voltage ripple within ±2%, and the energy efficiency of 46% are achieved

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“…To reduce the series resistance, multi-layer metals are used to construct the spiral inductor in parallel, [32,33,34,35]. In [33] for instance, the top metal and the underneath metal are connected to form a thicker conductor by shorting both metals using a via array.…”

Section: Spiral Inductormentioning

confidence: 99%

Characterization and modeling of silicon devices for RF applications

Teo¹

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Analysis on the effect of parallel current path on the quality factor of CMOS spiral inductors for 1–10 GHz

Cited by 6 publications

References 7 publications

Multilayer, Stacked Spiral Copper Inductors on Silicon with Micro-Henry Inductance Using Single-Level Lithography

Multilayer, Stacked Spiral Copper Inductors on Silicon with Micro-Henry Inductance Using Single-Level Lithography

A Fully-Integrated Buck Converter Design and Implementation for On-Chip Power Supplies

Characterization and modeling of silicon devices for RF applications

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