The influence of the ozone oxidation conditions on the interfacial and electrical properties of high-k/SiGe gate stacks was investigated by using a step-by-step fabrication procedure. The relationship between the electrical characteristics and the corresponding interfacial chemical structures revealed that a long oxidation time was necessary to obtain a high-quality interlayer (IL), whereas adverse in terms of interface state density (D it ) and equivalent oxide thickness (EOT) scaling. This conclusion suggested us to employ a posthigh-k-deposition oxidation (post-O) method to fabricate high-k/IL/SiGe gate stacks, in which the ozone oxidation was carried out after the deposition of the high-k layer. Compared with the step-by-step method, the post-O method could realize an ultrathin IL over a long oxidation time, owing to the reduced oxidation rate. Consequently, a well-balanced high-k/IL/SiGe gate stack with an ultrathin Ge-free IL of 0.26 nm, low gate leakage at V FB -1 of 6 × 10 −4 A/cm 2 , and D it as low as 2.2 × 10 12 eV −1 cm −2 was obtained.