In this paper, the optimization of SiGe interface property for SiGe channel FinFET transistor is explored in detail. First, an optimal low-temperature ozone oxidation at 300 ℃ for 30 min was confirmed based on the Al2O3/Si0.7Ge0.3 MOS capacitors. This is because that a higher oxidation temperature and a longer oxidation time could suppress the formation of GeOX in the interface layer (IL), and significantly improve interface state density (Dit). Moreover, compared with Al2O3 sample, HfO2 sample can obtain a thinner capacitance equivalent oxide thickness (CET), but it is more vulnerable to deterioration of Si0.7Ge0.3 interface property because the GeOX in the IL is more likely to diffuse into HfO2 layer. To further optimize the Dit and CET of Si0.7Ge0.3 MOS capacitor simultaneously, a stacked HfO2/Al2O3 dielectric is proposed. Compared with the HfO2 sample, its frequency dispersions characteristics and Dit have been improved significantly since the thin Al2O3 layer prevents the diffusion of GeOX to HfO2 layer and controls the growth of GeOX. Therefore, a high quality Si0.7Ge0.3 interface property optimization technology is realized by development of a low-temperature ozone oxidation (300 ℃, 30 min) combined with a stacked HfO2/Al2O3 dielectric. In addition, a Si0.7Ge0.3 FinFET utilizing this newly developed interface property optimization scheme is successfully prepared. Its excellent SS performance indicates that a good interface quality of the Si0.7Ge0.3 is obtained. The above result proves that these newly developed interface property optimization scheme is a practical technology for high mobility SiGe FinFET.
This article reviews advanced process and electron device technology of integrated circuits, including recent featuring progress and potential solutions for future development. In 5 years, for pushing the performance of fin field-effect transistors (FinFET) to its limitations, several processes and device boosters are provided. Then, the three-dimensional (3D) integration schemes with alternative materials and device architectures will pave paths for future technology evolution. Finally, it could be concluded that Moore's law will undoubtedly continue in the next 15 years.
The interface passivation of the HfO2/Si0.7Ge0.3 stack is systematically investigated based on low-temperature ozone oxidation and Si-cap methods. Compared with the Al2O3/Si0.7Ge0.3 stack, the dispersive feature and interface state density (Dit) of the HfO2/Si0.7Ge0.3 stack MOS (Metal-Oxide-Semiconductor) capacitor under ozone direct oxidation (pre-O sample) increases obviously. This is because the tiny amounts of GeOx in the formed interlayer (IL) oxide layer are more likely to diffuse into HfO2 and cause the HfO2/Si0.7Ge0.3 interface to deteriorate. Moreover, a post-HfO2-deposition (post-O) ozone indirect oxidation is proposed for the HfO2/Si0.7Ge0.3 stack; it is found that compared with pre-O sample, the Dit of the post-O sample decreases by about 50% due to less GeOx available in the IL layer. This is because the amount of oxygen atoms reaching the interface of HfO2/Si0.7Ge0.3 decreases and the thickness of IL in the post-O sample also decreases. To further reduce the Dit of the HfO2/Si0.7Ge0.3 interface, a Si-cap passivation with the optimal thickness of 1 nm is developed and an excellent HfO2/Si0.7Ge0.3 interface with Dit of 1.53 × 1011 eV−1cm−2 @ E−Ev = 0.36 eV is attained. After detailed analysis of the chemical structure of the HfO2/IL/Si-cap/Si0.7Ge0.3 using X-ray photoelectron spectroscopy (XPS), it is confirmed that the excellent HfO2/Si0.7Ge0.3 interface is realized by preventing the formation of Hf-silicate/Hf-germanate and Si oxide originating from the reaction between HfO2 and Si0.7Ge0.3 substrate.
The effect of As ion implantation on the stability of SiGe/Si multilayer was systematically studied. The atomic percentage of Ge in as-grown SiGe layer was 30% in this work. A thermally stable Si0.7Ge0.3/Si multilayer with As ion implantation was attained when the rapid thermal annealing (RTA) treatment temperature did not exceed 850 oC. Significant Ge diffusion was observed for the SiGe/Si multilayer with As ion implantation when the RTA temperature was 900 °C or above. However, minor Ge diffusion was attained for the SiGe/Si multilayer without As ion implantation when the RTA treatment temperature was 900 °C. Therefore, , compared with samples without As ion implantation, the stability window of the SiGe/Si multilayer with As ion implantation should be further reduced to 850 °C. As ion implantation plays a critical role in the stability of SiGe/Si multilayer, as it promotes the diffusion of Ge. Consequently, based on the stability of the SiGe/Si multilayer, the highest RTA treatment temperature of 850 °C is proposed for the gate-all-around (GAA) device fabrication process.
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