A fully integrated four-input combining receiver front-end circuit is designed in a 0.18 μm CMOS technology for laser radar with a static unitary detector (STUD). This circuit consists of four independent transimpedance amplifiers, one signal combiner, a balun and an output buffer in one single integrated chip. The circuit provides 16.2 mW power consumption for a 1.8 V supplied voltage and 59.8 dBΩ transimpedance gain in the implemented experimental prototype for electrical pulse measurement. The fabricated prototype is worked exactly the same as the operation principle of the STUD in the two-dimensional optical pulse scanning measurement. Therefore, the proposed circuit is available for the STUD-based laser detection and ranging (LADAR) system as one integrated chip. This is the first demonstrated IC for the STUD-based laser radar system. Introduction: Laser detection and ranging (LADAR) sensors are commonly used to acquire real-time three-dimensional (3D) images using the time-of-flight (TOF) of a short laser pulse. Since the LADAR technology has a potential to obtain the 3D images of the fast moving target, it has been deployed in many applications like reconnaissance, autonomous vehicles and robots, remote sensing, terrain visualisation, and surface mapping for buildings and scenes [1,2]. For the real-time acquisition of 3D images, LADAR systems need to process all reflected TOF laser signals from every direction for a region of interest (ROI) in real time.There are different operation methods of LADAR systems with varying scanning mechanisms, number of lasers and geometric configurations. Recently, a new technique for real-time 3D images acquisition using a static unitary detector (STUD) was reported [3]. In this method, a large-area photodetector is mainly utilised instead of using the rotational motion [4] or the focal-plane-array (FPA) [5]. Specially, to overcome the bandwidth limitation by large parasitic capacitance of the large-area photodetector, multiple partitioned photosensitive cells are adapted in the STUD to collect incident photons. In the STUD, each cell has an independent cascading transimpedance amplifier (TIA) which amplifies the received signals from each cell, and all the outputs of each TIA are summed by a signal combiner. Consequently, each of the partitioned photodetectors can be operated independently without affecting each other, which indicates that no bandwidth limitation exists even increasing the number of cells. To implement the STUD-based LADAR system, however, TIAs are needed as much as the number of partitioned photosensitive cells and they are assembled on a single board. This causes restriction in the number of cells for higher-resolution 3D images on a large ROI due to the interconnection problem between a partitioned photodetector and multiple TIAs.In this Letter, a fully integrated compact four-input combining receiver front-end circuit for the STUD-based LADAR system is first proposed. Generally, in a readout IC (ROIC) for the FPA-based LADAR, minimising crosstalk betwe...