No abstract

No abstract

No abstract

No abstract

No abstract

Several field-effect transistor (FET)-based device technologies are emerging as powerful alternatives to the classical metal oxide semiconductor FET (MOSFET) for computing applications. The focus of this study is on arithmetic circuit design in carbon nanotube FET (CNTFET) technology. In particular, the authors develop low-delay and low-power multi-ternary digit CNTFET-based adder designs. The proposed designs are based on unary operators of multi-valued logic. Efficient designs for primitives such as ternary half-adder (HA) and full-adder are developed and they are used to obtain low-complexity multi-digit adders based on the notions of conditional sum and carry lookahead. Extensive HSPICE simulations reveal that the powerdelay product of the proposed CNTFET-based HA and full-adder are roughly 20 and 50%, respectively, of that of recent designs. Further, the proposed CNTFET-based conditional sum adder has a power-delay product of approximately 27% of that of a multitrit design derived from a recent single-trit adder design (for a load capacitance of 2 fF). Moreover, the proposed CNTFET-based carry lookahead adder has low delay in comparison with the conditional sum strategy for different supply voltages. Studies on robustness of the designs are also reported. To our knowledge, there are no prior low-delay and low-power CNTFET-based multi-trit adder designs. Detailed HSPICE simulations using the MOSFET-like CNTFET library described in [16] reveal that i. The worst-case delay of the proposed CNTFET-based HA is roughly (i) 50% and (ii) 31%, respectively, of the delay for the designs in [7, 8]. Further, the proposed design has a powerdelay product (PDP) of approximately (i) 21% and (ii) 13%, respectively, of the designs in [7, 8]. ii. The proposed CNTFET-based full-adder has a PDP of approximately 50% of that of the design in [11]. iii. The proposed CNTFET-based HA and full-adder designs are highly robust. iv. The proposed CNTFET-based CSA has a PDP of approximately (i) 27% and (ii) 18%, respectively, of the PDP of multi-trit designs based on the single-trit adders in [8, 11] (for a load capacitance of 2 fF). v. The proposed CNTFET-based carry lookahead adder (CLA) has a worst-case delay of approximately (i) 46% and (ii) 15%, respectively, of that of the proposed CSA and a multi-trit

No abstract

No abstract