Carbon nanotube FET‐based low‐delay and low‐power multi‐digit adder designs

Abstract

Several field-effect transistor (FET)-based device technologies are emerging as powerful alternatives to the classical metal oxide semiconductor FET (MOSFET) for computing applications. The focus of this study is on arithmetic circuit design in carbon nanotube FET (CNTFET) technology. In particular, the authors develop low-delay and low-power multi-ternary digit CNTFET-based adder designs. The proposed designs are based on unary operators of multi-valued logic. Efficient designs for primitives such as ternary half-adder (HA) and full-adder are developed and they are used to obtain low-complexity multi-digit adders based on the notions of conditional sum and carry lookahead. Extensive HSPICE simulations reveal that the powerdelay product of the proposed CNTFET-based HA and full-adder are roughly 20 and 50%, respectively, of that of recent designs. Further, the proposed CNTFET-based conditional sum adder has a power-delay product of approximately 27% of that of a multitrit design derived from a recent single-trit adder design (for a load capacitance of 2 fF). Moreover, the proposed CNTFET-based carry lookahead adder has low delay in comparison with the conditional sum strategy for different supply voltages. Studies on robustness of the designs are also reported. To our knowledge, there are no prior low-delay and low-power CNTFET-based multi-trit adder designs. Detailed HSPICE simulations using the MOSFET-like CNTFET library described in [16] reveal that i. The worst-case delay of the proposed CNTFET-based HA is roughly (i) 50% and (ii) 31%, respectively, of the delay for the designs in [7, 8]. Further, the proposed design has a powerdelay product (PDP) of approximately (i) 21% and (ii) 13%, respectively, of the designs in [7, 8]. ii. The proposed CNTFET-based full-adder has a PDP of approximately 50% of that of the design in [11]. iii. The proposed CNTFET-based HA and full-adder designs are highly robust. iv. The proposed CNTFET-based CSA has a PDP of approximately (i) 27% and (ii) 18%, respectively, of the PDP of multi-trit designs based on the single-trit adders in [8, 11] (for a load capacitance of 2 fF). v. The proposed CNTFET-based carry lookahead adder (CLA) has a worst-case delay of approximately (i) 46% and (ii) 15%, respectively, of that of the proposed CSA and a multi-trit

Design of energy‐efficient ternary circuits using differential cascode voltage switch strategies in carbon nanotube field effect transistor technology

“…The proposed STI/STB circuits have 1.71 × and 1.42 × lower power and PDP as compared to best reported counterparts. Since no DCVS‐based shifting operators are existing, so the proposed designs are compared with the individual designs [18, 19]. Similarly, power and PDP improvement for STAND/NAND is and and for STOR/NOR is and , respectively, as compared to designs [4].…”

“…The design of the shifting operators utilising different realisation methods are listed in [18–21]. The single shift and dual shift operators of [18, 19] are optimised in terms of device count but have the problem of high static power dissipation. Pass transistor logic based shifting operators are described in [21].…”

Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology

“…At first, three ternary inverters are defined in the ternary logic, i.e., negative ternary inverter (NTI), positive ternary inverter (PTI) and standard ternary operator (STI), respectively [12]. Further permutative operations are defined performing the single shift (A(+1)), dual shift (A(+2)), self-shift (A( 12)) [26] and self-single shift (A(01)), respectively. These permutative operators are considered as the logical shift operations in ternary ALU block.…”

“…The miscellaneous block is used to process various basic unary operations such as A(+1), A(+2), A (12), A(01), buffer and inverter operators as mentioned in Table 1. These operators are used at the intermediate stage in the realization of complex circuits for those designs which do not apply ternary to binary and binary to ternary conversion approach to implement the ternary circuits [25,26]. Single shift (A(+1)) and dual shift (A(+2)) operator realization using 2:1 multiplexer design is depicted in Fig.…”

“…This is because the method adopted for the implementation is ternary to binary conversion using decoders and then all computations are carried out using binary gates and finally binary to ternary conversion is performed using encoders/buffer circuits. Ternary arithmetic circuits such as adder, subtractor and multiplier designs using the aforementioned approach are described in [12,13,20,21,24,31].Ternary arithmetic circuits based on a direct method, where directly the data processing occurs on the ternary values, are explained in [2,7,9,[25][26][27].…”