Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity

Design and Analysis of Majority Logic-Based Approximate Adders and Multipliers

“…A comparison in terms of number of majority gates (MV), number of inverters (INV), NMED, MAE, delay (D) and delay of carry (D carry ) between EFA, MLAFA1 [12] and the proposed MLAFA2 is reported in Table 2. When considering ML based nanotechnologies, delay (as assessed in this paper) is normalized by the number of majority gates only (so, the delay for the inverters is not included because it is often very small compared to the ML gate) [17]. Compared with EFA, MLAFA2 saves two majority gates, one inverter and one delay.…”

“…The exact expressions for the outputs in these eight cases are given in Eqs. (15)- (17); the schematic diagram is illustrated in Fig. 5(e), this design is hereafter referred to as MLAFA33.…”

A Parallel-friendly Majority Gate to Accelerate In-memory Computation

“…For this work, we choose Ladner-Fischer since it minimizes logical depth at the cost of fan-out (fan-out of a gate translates to WRITE, as will be elaborated in section IV-B). Since majority gate is the basic building block for many emerging nanotechnologies, prior works [11], [12] have formulated such PP adders in terms of majority gates. The carry-generate and sum-generate blocks for an eight-bit adder in majority logic are derived from [11], [12] (Fig.…”

“…Fig. 8: Eight-bit PP adder (Ladner-Fischer)expressed as 7 levels of majority and NOT gates [11], [12]. Majority gates 1-20 constitute carry generate block and 21-36 constitute sum generate block.…”

“…Although majority logic was known since 1960, there has been a revival in using it for computation in many emerging nanotechnologies (spin waves, magnetic Quantum-Dot cellular automata, nano magnetic logic, Single Electron Tunneling). Recent research [10]- [12] has confirmed that majority logic is to be preferred not only because a particular nanotechnology can realize it, but also because of its ability to implement arithmetic-intensive circuits with less gates. It must be emphasized that majority logic did not become the dominant logic to compute because it was more efficient to implement NAND/NOR gate than a majority gate, in CMOS technology.…”