A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies

Srinivasu, B.; Sridharan, K.

doi:10.1109/tcsi.2017.2686446

Cited by 69 publications

(64 citation statements)

References 34 publications

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“…Table III shows comparison of the normalized worst delay, average power, and PDP results between ternary multipliers. From the results, we can see that our proposed design has significantly reduced the data path delay and required number of devices compared to design in [7]. Our proposed design shows 62 % PDP reduction compared to the previous work [7].…”

Section: Ternary Multiplier Design and Simulation Resultsmentioning

confidence: 75%

“…From the results, we can see that our proposed design has significantly reduced the data path delay and required number of devices compared to design in [7]. Our proposed design shows 62 % PDP reduction compared to the previous work [7]. We have also implemented a single trit multiplier based on the balanced ternary logic.…”

Section: Ternary Multiplier Design and Simulation Resultsmentioning

confidence: 91%

“…Table II compares the normalized worst delay, average power, and PDP results of ternary full adder. Our proposed design shows 49 % PDP reduction compare to the design of [7], which is based on a transmission gate. Moreover, our proposed design shows 79 % PDP reduction compare to the design of [11].…”

Section: Ternary Full Adder Design and Simulation Resultsmentioning

confidence: 91%

“…However, the proposed designs have been optimized for specific circuits such as ternary adders and ternary multipliers, making it difficult to optimally implement ternary logic circuits at the system level. Recently, a ternary logic synthesis methodology based on multiplexers using a transmission gate has been proposed to synthesize a general logic design [7]. However, transmission gates have worse power, speed, and noise margin than static gates.…”

Section: Introductionmentioning

confidence: 99%

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An optimal gate design for the synthesis of ternary logic circuits

Kim

Lim

Kang

2018

2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)

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Over the last few decades, CMOS-based digital circuits have been steadily developed. However, because of the power density limits, device scaling may soon come to an end, and new approaches for circuit designs are required. Multi-valued logic (MVL) is one of the new approaches, which increases the radix for computation to lower the complexity of the circuit. For the MVL implementation, ternary logic circuit designs have been proposed previously, though they could not show advantages over binary logic, because of unoptimized synthesis techniques. In this thesis, we propose a methodology to design ternary gates by modeling pull-up and pull-down operations of the gates. Our proposed methodology makes it possible to synthesize ternary gates with a minimum number of transistors. From HSPICE simulation results, our ternary designs show significant power-delay product reductions; 49 % in the ternary full adder and 62 % in the ternary multiplier compared to the existing methodology. We have also compared the number of transistors in CMOSbased binary logic circuits and ternary device-based logic circuits We propose a methodology for using ternary values effectively in sequential logic. Proposed ternary D flip-flop is designed to normally operate in four-edges of a ternary clock signal. A quad-edgetriggered ternary D flip-flop (QETDFF) is designed with static gates using CNTFET. From HSPICE simulation results, we have confirmed that power-delay-product (PDP) of QETDFF is reduced by 82.31 % compared to state of the art ternary D flip-flop. We synthesize a ternary serial adder using QETDFF. PDP of the proposed ternary serial adder is reduced by 98.23 % compared to state of the art design.

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Section: Ternary Multiplier Design and Simulation Resultsmentioning

confidence: 75%

Section: Ternary Multiplier Design and Simulation Resultsmentioning

confidence: 91%

Section: Ternary Full Adder Design and Simulation Resultsmentioning

confidence: 91%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An optimal gate design for the synthesis of ternary logic circuits

Kim

Lim

Kang

2018

2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)

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“…The mixed-polarity RM (MPRM) logic circuit is a standard form of the RM logic circuit [4,5]. Area optimization presents a crucial problem for the MPRM logic circuit [6,7] and is the key step in logic synthesis in RM circuits [8]. Area optimization of the MPRM logic circuit is a nondeterministic polynomial time (NP) complete problem [9,10].…”

Section: Introductionmentioning

confidence: 99%

Verification Method for Area Optimization of Mixed-Polarity Reed-Muller Logic Circuits

Chen

Lin

Zhu³

2018

JESTR

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Area minimization of mixed-polarity Reed-Muller (MPRM) logic circuits is an important step in logic synthesis. While previous studies are mainly based on various artificial intelligence algorithms and not comparable with the results from the mainstream electronics design automation (EDA) tool. Furthermore, it is hard to verify the superiority of intelligence algorithms to the EDA tool on area optimization. To address these problems, a multi-step novel verification method was proposed. First, a hybrid simulated annealing (SA) and discrete particle swarm optimization (DPSO) approach (SADPSO) was applied to optimize the area of the MPRM logic circuit. Second, a Design Compiler (DC) algorithm was used to optimize the area of the same MPRM logic circuit under certain settings and constraints. Finally, the area optimization results of the two algorithms were compared based on MCNC benchmark circuits. Results demonstrate that the SADPSO algorithm outperforms the DC algorithm in the area optimization for MPRM logic circuits. The SADPSO algorithm saves approximately 9.1% equivalent logic gates compared with the DC algorithm. Our proposed verification method illustrates the efficacy of the intelligence algorithm in area optimization compared with DC algorithm. Conclusions in this study provide guidance for the improvement of EDA tools in relation to the area optimization of combinational logic circuits.

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An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology

Abbasian,

Orouji,

Taghipour Anvari

et al. 2023

Circuit Theory & Apps

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SummaryInternet‐of‐Things (IoTs)‐based embedded systems require energy‐efficient designs for long‐term operation. To achieve energy‐efficient designs, multiple‐valued logic (MVL) circuits and graphene nanoribbon field‐effect transistors (GNRFETs) are used instead of binary logic circuits and complementary metal‐oxide‐semiconductor (CMOS), respectively. This paper presents a novel ultra‐low power and energy‐efficient ternary Half‐Adder (THA) circuit based on unary operators, two power supplies (dual‐VDD), VDD and VDD/2, and two ternary 3:1 multiplexers in 32 nm GNRFET technology. The superiority of the proposed design are improvements between 2.86% and 60% in transistor count, between 86.12% and 97.15% in power consumption, and between 58.14% and 98.39% in power‐delay‐product (PDP) compared to existing THA circuits. Moreover, the proposed THA circuit is also implemented with 32 nm carbon nanotube field‐effect transistors (CNTFETs). Simulation results indicate that the proposed GNRFET‐based THA circuit increases delay by 1.74 × and reduces power/PDP by 89.41%/81.63% compared to its CNTFET‐based counterpart.

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A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies

Cited by 69 publications

References 34 publications

An optimal gate design for the synthesis of ternary logic circuits

An optimal gate design for the synthesis of ternary logic circuits

Verification Method for Area Optimization of Mixed-Polarity Reed-Muller Logic Circuits

An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology

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