Efficient Multiternary Digit Adder Design in CNTFET Technology

Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology

“…Table 3 shows the simulation results of ternary arithmetic circuits at 0.9 V power supply and room temperature with 1fF output load. According to the simulation results, the proposed HA and HASE has great improvement in power by 91%, with increase in delay by only 12% and 24% respectively, compared to the HA of (Sridharan et al, 2013). Similarly, the proposed 1-bit multiplier achieves improvement in power by 90% with only 2% increase in delay compared to its counterpart of (Sridharan et al, 2013).…”

“…The decoder design presented in (Sridharan et al, 2013) is utilized to generate unary functions (and their complements) for an applied ternary input. Next, function selection logic block is used for the selection of one particular ALU function based on the status of the select signals S1 and S0, as described in Table 2.…”

“…These transistors with identical parameters perform voltage division and produce output equal to (X 1 + X 2 )/2, as described in truth table of encoder shown in Figure 4. The proposed design uses pass transistor logic and thereby, eliminates a direct path from V dd to ground which results in less power dissipation compared to the encoder of (Sridharan et al, 2013). Thus, it leads to the low power designs of various TALU modules (as shown later).…”

“…A power delay product (PDP), which is defined as the multiplication of average power dissipation and maximum delay, is also computed to evaluate the performance of the design in terms of energy efficiency. Since the FA design of (Sridharan et al, 2013) outperforms other CMOS and CNTFET based designs, HA and 1-bit multiplier are also implemented by using the same design methodology and referred as HA of (Sridharan et al, 2013) and 1-bit multiplier of (Sridharan et al, 2013), respectively, here. Table 3 shows the simulation results of ternary arithmetic circuits at 0.9 V power supply and room temperature with 1fF output load.…”

“…A CNTFET-based 2-bit ternary arithmetic logic unit (TALU) has also been proposed in (Murotiya & Gupta 2013), which is optimized at architecture as well as at circuit level and leads to a hardware efficient design. Recently, some CNTFET-based ternary arithmetic and logic circuits have been proposed in (Sridharan, Gurindagunta, & Pudi, 2013) and (Vudadha, Phaneendra, Sreehari, & Srinivas, 2012), which outperform the previously presented CMOS and CNTFET-based ternary circuits, and therefore, used for comparison in this paper.…”