Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology

Murotiya, Sneh Lata; Gupta, Anu

doi:10.1080/00207217.2015.1082199

Cited by 11 publications

(34 citation statements)

References 28 publications

(42 reference statements)

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Section: Proposed Ternary Alu Architecture and Functionalitymentioning

confidence: 99%

“…The T-ALU designs presented in [5,14,15] are based on ternary function minimization and exploits the K-map in order to reduce the ternary functions. The ALU designs [14,15] are an improved version of [5] in terms of hardware and circuit parameters. For the function select logic block, design [15] uses NAND gates and the decoders [13], while design [14] uses arrays of AND gates together with the decoder outputs [13].…”

Section: Proposed Ternary Alu Architecture and Functionalitymentioning

confidence: 99%

“…The ALU designs [14,15] are an improved version of [5] in terms of hardware and circuit parameters. For the function select logic block, design [15] uses NAND gates and the decoders [13], while design [14] uses arrays of AND gates together with the decoder outputs [13]. While in the proposed ALU design, function selection is performed using two-level multiplexing with the help of a ternary multiplexer circuit.…”

Section: Proposed Ternary Alu Architecture and Functionalitymentioning

confidence: 99%

“…The design is constructed using decoders [12], binary and ternary NAND gates, transmission gate blocks. In [15], one more modified version of T-ALU [14] is presented which combines adder, subtractor and Ex-OR in a single module. Further encoder circuits are used rather than ternary buffers in order to realize the ternary outputs.…”

Section: Introductionmentioning

confidence: 99%

“…Further encoder circuits are used rather than ternary buffers in order to realize the ternary outputs. The designs [14,15] are free from the problem of large off-chip resistors, but the overall hardware complexity of the design is high. This is because the method adopted for the implementation is ternary to binary conversion using decoders and then all computations are carried out using binary gates and finally binary to ternary conversion is performed using encoders/buffer circuits.…”

Section: Introductionmentioning

confidence: 99%

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Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology

Sharma

Kumre

2019

Circuits Syst Signal Process

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This article presents the low-power ternary arithmetic logic unit (ALU) design in carbon nanotube field-effect transistor (CNFET) technology. CNFET unique characteristic of geometry-dependent threshold voltage is employed in the multi-valued logic design. The ternary logic benefit of reduced circuit overhead is exploited by embedding multiple modules within a block. The existence of symmetric literals among various single shift and dual shift operators in addition and subtraction operations results in the optimized realization of adder/subtractor modules. The proposed design is based on the notion of multiplexing either arithmetic, logical or miscellaneous operations, depending upon the status of input selection trits. The results obtained by the synopsis HSPICE simulator with the Stanford 32 nm CNFET technology illustrate that the proposed processing modules outperform their counterparts in terms of power consumption, energy consumption and device count. The proposed methodology leads to saving in power consumption and energy consumption (PDP) of 62% and 58%, respectively, on the benchmark circuit of the ALU [full adder/subtractor (FAS)]. Furthermore, for the 2-trit multiplier design, the enhanced performance at the architecture and circuit level is achieved through the optimized designs of various adder and multiplier circuits. KeywordsCarbon nanotube field-effect transistor (CNFET) • Multi-valued logic design • Ternary ALU • Nano-technology • Low power B Trapti Sharma

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Section: Proposed Ternary Alu Architecture and Functionalitymentioning

confidence: 99%

Section: Proposed Ternary Alu Architecture and Functionalitymentioning

confidence: 99%

Section: Proposed Ternary Alu Architecture and Functionalitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology

Sharma

Kumre

2019

Circuits Syst Signal Process

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Design implementations of ternary logic systems: A critical review

Zahoor,

Jaber,

Isyaku

et al. 2024

Results in Engineering

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Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

Nemati

Kashani

Mirzaee

2023

IET Circuits, Devices & Syst

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The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or V DD . This way, in a single-V DD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count. K E Y W O R D Sadders, carbon nanotube field effect transistors, digital arithmetic, multivalued logic, multivalued logic circuits, ternary logicThis is an open access article under the terms of the Creative Commons Attribution-NonCommercial License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited and is not used for commercial purposes.

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Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology

Cited by 11 publications

References 28 publications

Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology

Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology

Design implementations of ternary logic systems: A critical review

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

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