Low-Complexity Multiternary Digit Multiplier Design in CNTFET Technology

Srinivasu, B.; Sridharan, K.

doi:10.1109/tcsii.2016.2531100

Cited by 44 publications

(45 citation statements)

References 17 publications

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“…The proposed decoder, a half adder and a 1-digit multiplier, as well as the latest published works [12] and [14]- [18] have been simulated through HSPICE [19] in 32nm technology by applying the Stanford compact model for CNTFET [20] and keeping the same voltages and parasitic capacitances.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Also, the transistor count of the proposed decoder is 6, while the transistor counts of designs [15] and [17] are 8 and 9 respectively. The proposed half adder and 1-digit multiplier are compared with [12] and [14]- [18] designs at 1 GHz frequency, 0.9 V supply voltage, 3.5 fF load capacitance, 20 ps rise, 20 ps fall time scenario and 25 • C temperature conditions in Table 8 and 9 respectively, showing transistor count, power consumption, delay, PDP and power supply count.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Several studies have designed different ternary CNTFETbased circuits; the primary arithmetic circuits presented in these works are of the types half adder and 1-digit multiplier, focusing on the implementation of efficient circuits in terms of transistor count [7], [8], delay [12] and power, [14]- [18]. A ternary half adder has been designed by applying a ternary decoder and basic ternary logic gates by Dhande and Ingole [8].…”

Section: Previous Workmentioning

confidence: 99%

“…Further designs of a ternary half adder and a 1-digit multiplier using pass transistors with a lower transistor count, but high power consumption and delay have also been proposed by Srinivasu and Sridharan [14].…”

Section: Previous Workmentioning

confidence: 99%

“…A similar procedure can be applied for the implementation of any other logic block. The results of the implementation for a 1-digit multiplier (a typical logic block reported in [14] and [17]), following the methodology from section IV is presented in the next section.…”

Section: Detailed Implementation Of Ternary Half Addermentioning

confidence: 99%

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A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells

2020

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The huge quantity of nodes and interconnections in modern binary circuits leads to extremely high levels of energy consumption. The interconnection complexity and other issues of binary circuits encourage researchers to consider multiple-valued logic (MVL) alternatives. Features of Carbon Nanotube Field-Effect Transistors (CNTFETs) make this technology a potential candidate to implement MVL circuits. In this article, a new systematic methodology is proposed to design ternary logic block circuits based on CNTFETs. The methodology is applied to the design of two basic logic circuits, a half adder and a 1-digit multiplier, which are evaluated through HSPICE simulations. Simulation results indicate improvements over current equivalents in transistor count and PDP mean with the half adder version of 19.2%, and 74.07% respectively, and with the 1-digit multiplier of 24.67% and 81.12% respectively.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Simulation Resultsmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

Section: Detailed Implementation Of Ternary Half Addermentioning

confidence: 99%

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A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells

2020

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An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology

Abbasian,

Orouji,

Taghipour Anvari

et al. 2023

Circuit Theory & Apps

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SummaryInternet‐of‐Things (IoTs)‐based embedded systems require energy‐efficient designs for long‐term operation. To achieve energy‐efficient designs, multiple‐valued logic (MVL) circuits and graphene nanoribbon field‐effect transistors (GNRFETs) are used instead of binary logic circuits and complementary metal‐oxide‐semiconductor (CMOS), respectively. This paper presents a novel ultra‐low power and energy‐efficient ternary Half‐Adder (THA) circuit based on unary operators, two power supplies (dual‐VDD), VDD and VDD/2, and two ternary 3:1 multiplexers in 32 nm GNRFET technology. The superiority of the proposed design are improvements between 2.86% and 60% in transistor count, between 86.12% and 97.15% in power consumption, and between 58.14% and 98.39% in power‐delay‐product (PDP) compared to existing THA circuits. Moreover, the proposed THA circuit is also implemented with 32 nm carbon nanotube field‐effect transistors (CNTFETs). Simulation results indicate that the proposed GNRFET‐based THA circuit increases delay by 1.74 × and reduces power/PDP by 89.41%/81.63% compared to its CNTFET‐based counterpart.

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