A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells

Abstract

The huge quantity of nodes and interconnections in modern binary circuits leads to extremely high levels of energy consumption. The interconnection complexity and other issues of binary circuits encourage researchers to consider multiple-valued logic (MVL) alternatives. Features of Carbon Nanotube Field-Effect Transistors (CNTFETs) make this technology a potential candidate to implement MVL circuits. In this article, a new systematic methodology is proposed to design ternary logic block circuits based on CNTFETs. The methodology is applied to the design of two basic logic circuits, a half adder and a 1-digit multiplier, which are evaluated through HSPICE simulations. Simulation results indicate improvements over current equivalents in transistor count and PDP mean with the half adder version of 19.2%, and 74.07% respectively, and with the 1-digit multiplier of 24.67% and 81.12% respectively.

Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders

“…The proposed ternary unary operators, THA, and TMUL are validated, simulated, and compared to 32 nm channel CNTFET-Based ternary circuits in [15]- [23], [25], [27], [29], [31]- [34] using the HSPICE simulator.…”

“…So as explained above, the proposed designs reduce the power consumption more than 90% compared to [15]- [21] that use diode-connected transistors and between 6% and 60% reduction compared to [29], [31], [33], [34] that do not use diode-connected transistors.…”

“…(5) Use transmission gates (TGs) in series, special transistors arrangements, or Resistive Random Access Memory (RRAM) such as: Authors of [28], [29] proposed THAs with (39 and 50 CNT-FETs) and TMULs with (34 and 38 CNTFETs) using cascading TGs, which produced higher propagation delays and PDP. In [30], the authors proposed THA with 90 CNTFETs and TMUL with 62 CNTEFTs using RRAM.…”

Recent Advances on Multivalued Logic Gates: A Materials Perspective

“…The universal logic gates, ternary NAND and NOR gates, therefore have the same complexity as the ternary inverters according to de Morgan's law, which enables dissociation of positive and negative binary operators (NAND and NOR gates, respectively) into two positive or two negative unary operators (NOT gates). [ 45 ] For simplicity, we review the operation and design of the simplest MVL gate, STI, throughout this report. The material and device criteria used in the realization of the STI can be expanded to higher‐level operators by using complex circuit‐level designs.…”

“…For example, a combination of enhancementmode and depletion-mode complementary MOS (CMOS) devices was used to design multithreshold-voltage logic gates such as a simple ternary inverter (STI), positive ternary inverter (PTI), and negative ternary inverter (NTI). [42][43][44][45] However, the incompatibility of these devices with the existing CMOS technology and the higher number of interconnections required in the construction of basic logic functions were major bottlenecks in ensuring the comparative superiority of these devices to the existing binary-logic-based technology. Naturally, the essentiality of mitigating those issues highlighted the necessity for devising de novo approaches that can provide not only high information density but also high area efficiency or energy efficiency at the device level.…”