However, most of these devices are complex to fabricate or operate at cryogenic temperatures. More recently, ternary devices based on various low-dimensional materials, such as carbon nanotubes, [20][21][22] graphene, [23][24][25][26][27][28] and 2D materials, have been developed. [29][30][31][32][33][34] These ternary devices are classified into two groups according to their operating mechanism. One group is based on negative differential resistance (NDR). [29][30][31][32][33][34] The NDR devices exhibit a current peak with increasing bias voltage, which is used to implement a ternary inverter with three logic states. The other group is based on multi-threshold voltages (V th ). [20][21][22][23][24][25][26][27][28] Two field-effect transistors (FETs) with different V th connected in parallel provide transfer curves with three current levels, and these ternary devices are used to demonstrate a ternary inverter. In addition to various ternary devices, other devices, such as two-terminal resistive switching devices [35] and optical memory devices based on 2D materials, [36] have been used to generate more than ten logic states. [37] However, despite the rapid progress in the field of MVL, there are few reports to demonstrate integrated circuits consisting of ternary devices or MVL devices due to the limitation of device uniformity and the difficulty in adjusting intermediate states.Herein, we report a ternary device based on a partially aligned MoS 2 -based flash memory device (Figure 1). When a channel of MoS 2 was fully aligned with a floating gate of graphene, large hysteresis with binary states was observed in the transfer curves, as reported by others. [36,38,39] However, when the MoS 2 channel was partially aligned with the graphene floating gate, the transfer curve exhibited hysteresis with two different values of V th and three current levels because the partially aligned MoS 2 -based flash memory device acted as a parallelly connected circuit consisting of a memory device and a FET. The memory and transistor components of the partially aligned MoS 2 -based flash memory devices could be clearly discriminated in the electrostatic force microscope (EFM) images. Unlike the reported ternary devices consisting of two FETs externally connected in parallel, [20,21,40,41] our devices are composed of a memory device and a FET internally connected in parallel; thus, compared to the reported devices, our device offers an opportunity to further decrease the chip area. Furthermore, an intermediate state determined by the resistance The development of multi-valued logic devices, which involve switching between more than two states, is one of the promising approaches for overcoming the issues caused by the further scaling down of the current complementary metal-oxide semiconductor devices. This paper presents ternary devices based on MoS 2 /h-BN/graphene heterostructures, in which an active channel of MoS 2 is partially aligned with a floating gate of graphene, unlike in the case of typical flash memory devices; thus, the...