The spatial resolution of scanning spreading resistance microscopy has been limited by using conventional probes when measuring in air. Sufficient electric contact of a probe-sample has been difficult to obtain in air due to the existence of moisture/contamination. Two-dimensional carrier profiling of nanoscale silicon devices is performed in a vacuum with conventional probes, and a high spatial resolution is obtained. Ultrashallow junctions down to 10nm are measured accurately with high reproducibility. Experimental results show that a good electric contact between probe and sample is important for obtaining high spatial resolution.

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An ovel series of C12-keto-type saxitoxin (STX) derivatives bearinga nu nusualn onhydrated form of the ketone at C12 has been synthesized,a nd their Na V -inhibitory activity has been evaluated in ac ell-based assay as well as whole-cell patch-clamp recording. Among these compounds, 11-benzylidene STX (3a)s howedp otent inhibitory activity againstn euroblastoma Neuro2Ai nboth cell-baseda nd electrophysiological analyses,w ithE C 50 and IC 50 valueso f8 .5 and 30.7 nm,r espectively.I nterestingly,t he compound showed potent inhibitory activity against tetrodotoxin-resistant subtype of Na V 1.5, with an IC 50 value of 94.1 nm.D erivatives 3a-d and 3f showedl ow recovery rates from Na V 1.2 subtype (ca4 5-79 %) comparedt on atural dcSTX (2), strongly suggesting an irreversible mode of interaction. We propose an interaction model for the C12-ketod erivatives with Na V in which the enonem oiety in the STX derivatives 3 worksa sM ichaela cceptorf or the carboxylateo fA sp 1717 .

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High performance 14 nm gate length CMOSFETs are demonstrated in this paper. To acquire shallow sourcddrain ( S D ) extension profile, the optimization of low thermal budget process utilizing poly-SiGe and Ni salicide is performed. A poly-SiGe gate electrode minimizes gate depletion effect, therefore high level of dopant activation in the gate electrode is realized even by low temperature spike annealing. Moreover, short channel characteristics are optimized by using offset spacer beside the gate electrode. The highest drive current is achieved in 14 nm gate length CMOSFETs reported to date.