BackgroundStigma towards people with mental health problems (PMHP) is known to have substantial negative impacts on their lives. More in-depth exploration of the stigma and discrimination experienced by PMHP in low- and middle-income countries is needed. Previous research suggests that negative attitudes towards PMHP are widespread among the Filipino general public. However, no study has investigated PMHP’s own experiences of being stigmatised in the Philippines.MethodsA qualitative study was conducted on the stigma experienced by PMHP (including people with epilepsy) and its related factors in the Philippines, employing the constructivist grounded theory approach. We analysed data on 39 PMHP collected through interviews with PMHP, their carers, and community health volunteers who know them well.ResultsThe findings highlight the culturally and socio-economically specific contexts, consequences, and impact modifiers of experiences of stigma. Participants emphasised that PMHP face stigma because of the cultural traits such as the perception of mental health problem as a disease of the family and the tendency to be overly optimistic about the severity of the mental health problem and its impact on their life. Further, stigma was experienced under conditions where mental health care was not readily available and people in the local community could not resolve the PMHP’s mental health crisis. Stigma experiences reduced social networks and opportunities for PMHP, threatened the economic survival of their entire family, and exacerbated their mental health problems. An individual’s reaction to negative experiences can be fatalistic in nature (e.g. believing in it is God’s will). This fatalism can help PMHP to remain hopeful. In addition, traditional communal unity alleviated some of the social exclusion associated with stigma.ConclusionsThe study indicates that existing stigma-reduction strategies might have limitations in their effectiveness across cultural settings. Therefore, we propose context-specific practical implications (e.g. emphasis on environmental factors as a cause of mental health problems, messages to increase understanding not only of the possibility of recovery but also of challenges PMHP face) for the Philippines.Electronic supplementary materialThe online version of this article (10.1186/s12888-018-1902-9) contains supplementary material, which is available to authorized users.

High-performance operation was achieved in a novel Schottky-source/drain MOSFET (SBT: Schottky Barrier Transistor), which has dopant-segregation (DS) Schottky source/drain. Sub-100 nm complementary DS-SBTs were fabricated using the CoSi 2 process, which was fully compatible with the current CMOS technology. Excellent CMOS performance was obtained without any channel-mobility degradation, and CMOS ring oscillator was successfully demonstrated. In addition, >20 % improvement in drive current over the conventional n-MOSFETs was confirmed in the n-type DS-SBTs around the gate length of 50 nm.

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We systematically study short-channel performance, threshold voltage variability, and negative bias temperature instability in silicon tri-gate nanowire transistors (NW Tr.). By introducing epi S/D with thin gate spacer, on-current of NW Tr. is significantly improved for the same off-current thanks to the parasitic resistance (R SD ) reduction. <100>-oriented NW channel further improves on-current as compared to <110> NW channel.In Pelgrom plot of σ σ σ σV th of NW Tr., there exists a universal line whose A vt is smaller than planar Tr. due to gate grain alignment.Deviation of the narrowest Tr. from σ σ σ σV th universal line is eliminated by suppressing R SD . Enhanced degradation by negative bias temperature stress in narrow NW Tr. can be attributed to the electric field concentration at the NW corner.

Temperature rise by self-heating effects in nanowire (NW) transistors (NW Trs.) is systematically studied with respect to their dependence on the structural parameters. Temperature rise in NW Tr. is found to be independent of the NW size in sub-100-nm regions when compared at the same total power consumption. This is because the heat generated by the drain current is spread to the area larger than the NW channel. Dependences of temperature rise on other parameters such as gate oxide or buried oxide thickness suggest that heat dissipates mainly via source/drain or substrate not via the gate electrode.Index Terms-Self-heating effect (SHE), silicon nanowire (NW) transistor (NW Tr.), silicon on insulator (SOI).

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We experimentally study the random telegraph noise (RTN) in nanowire transistor (NW Tr.) with various widths (W), lengths (L), and heights (H). Time components of RTN such as time to capture (τ c ) and emission (τ e ) are independent of NW size, while threshold voltage fluctuation (ΔV th ) by RTN can be well fitted with 1/{L(W+2H)} 0.5 corresponding to the conventional carrier number fluctuations regardless of the side surface orientation. Hot carrier injection (HCI) and negative bias temperature instability (NBTI) induced additional carrier traps leading to the increase in the number of observed RTN. Moreover, ΔV th is enhanced by HCI and NBTI and enhancement of ΔV th becomes larger in narrower W. IntroductionRTN caused by the carrier trap becomes a crucial issue in nano-scaled Tr. So far, RTN in NW Tr. has been reported [1]. Most of the reported RTN in NW Tr. were focused on each capture and emission behavior and often suggested the quantum confinement effect. However it is necessary to measure a number of RTN in order to conclude whether RTN in NW Tr. can be explained by the conventional size dependence as planar Tr. or not. Furthermore, it was reported that HCI and BTI, which are also the issues for reliabilities, induced the additional traps generating RTN [2,3]. Since HCI and NBTI degradations are enhanced in NW Tr. [4,5], RTN after HCI and NBTI should be investigated.In this work, we measured the NW size dependence and the side surface orientation dependence of RTN with a number of ment of Nanoelectronic Device Technology. The authors thank Dr. J.Chen for technical support.