10nm-diameter tri-gate silicon nanowire MOSFETs with enhanced high-field transport and V&lt;inf&gt;th&lt;/inf&gt; tunability through thin BOX

Saitoh, Masumi; Ota, Ken‐ichiro; Tanaka, Chika; Uchida, Ken; Numata, T.

doi:10.1109/vlsit.2012.6242436

Cited by 19 publications

(12 citation statements)

References 2 publications

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“…These devices possess improved controllability over lower leakage currents, SCEs and better yield. The performance can also be improved by varying the thickness of the oxide layer [1][2][3][4][5].…”

Section: Introductionmentioning

confidence: 99%

Influence of oxide thickness variation on analog and RF performances of SOI FinFET

Tripathy

Acharya

Rout³

et al. 2022

FACTA U EE

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This paper focuses on the impact of variation in the thickness of the oxide (SiO2) layer on the performance parameters of a FinFET analysed by varying the oxide layer thickness in the range of 0.8nm to 3nm. While varying the oxide layer thickness, the overall width of the FinFET is fixed at a value 30nm, and the FinFET parameters are analysed for structures with different oxide layer thickness. The parameters like drain current, transconductance, transconductance generation factor, parasitic capacitances, output conductance, cut-off frequency, maximum frequency, GBW, energy and power consumption are calculated to study the influence of FinFET oxide (SiO2) layer thickness variation. It is detected from the result and analysis that the drain current, transconductance, transconductance generation factor, gain bandwidth and output conductance improve with decrement in oxide layer thickness whereas, the parasitic capacitances, cut-off frequency and maximum frequency degrade when there is a reduction in oxide (SiO2) layer thickness. The parameters like energy and consumed power of FinFET get better when the oxide (SiO2) layer thickness increases.

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Section: Introductionmentioning

confidence: 99%

Influence of oxide thickness variation on analog and RF performances of SOI FinFET

Tripathy

Acharya

Rout³

et al. 2022

FACTA U EE

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“…Hence, SOI based FinFETs are the center of attraction now-a-days. The detail study of the SOI based FinFETs are presented in [19][20][21][22][23][24].…”

Section: Introductionmentioning

confidence: 99%

Influence of Variation in Oxide layer Thickness on Analog and RF performances of SOI FinFET

Tripathy

Pk³

2021

Preprint

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In this paper, the influence of oxide (SiO2) layer thickness on the different figure of merits of a FinFET is analysed by varying the oxide layer thickness which is present between the gate and the Fin. Here, the overall thickness of the FinFET is taken to be 30nm, and the oxide (SiO2) layer thickness is changed from 0.8 nm to 3nm, and the analog, radio frequency parameters are determined for different structures. The performance parameters like drain current (ID), transconductance generation factor (TGF), transconductance (gm), output conductance (gds), parasitic capacitances like Cgs, Cgd, Cgg, cut-off frequency (fT), gain bandwidth product (GBW) and maximum frequency of oscillation (fmax) are calculated to learn the influence of variation in the FinFET oxide (SiO2) layer thickness. It is detected from the result and analysis that the drain current, output conductance, transconductance generation factor, transconductance and gain bandwidth product improve with decrement in oxide layer thickness. But as a tradeoff, the internal capacitances like Cgs, Cgd, Cgg, maximum frequency of oscillation and cut-off frequency degrade when there is a reduction in oxide (SiO2) layer thickness.

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“…Polycrystalline silicon (poly-Si) nanowire (NW) thin film transistors (TFTs) have attracted much attention as key components in three-dimensional LSI. [1][2][3][4][5][6][7] With increasing mean grain size, the performance of poly-Si NW TFTs has improved and approached that of bulk-Si transistors. 7) For such poly-Si NW TFTs with a gate size smaller than the mean grain size of poly-Si, it is considered that the variation in the number of grain boundaries (GBs) inside channels induces characteristic variations.…”

Section: Introductionmentioning

confidence: 99%

Individual analysis of inter and intragrain defects in electrically characterized polycrystalline silicon nanowire TFTs by multicomponent dark-field imaging based on nanobeam electron diffraction two-dimensional mapping

Asano¹,

Takaishi²,

Oda³

et al. 2018

Jpn. J. Appl. Phys.

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We visualize the grain structures for individual nanosized thin film transistors (TFTs), which are electrically characterized, with an improved data processing technique for the dark-field image reconstruction of nanobeam electron diffraction maps. Our individual crystal analysis gives the oneto-one correspondence of TFTs with different grain boundary structures, such as random and coherent boundaries, to the characteristic degradations of ON-current and threshold voltage. Furthermore, the local crystalline uniformity inside a single grain is detected as the difference in diffraction intensity distribution.

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10nm-diameter tri-gate silicon nanowire MOSFETs with enhanced high-field transport and V<inf>th</inf> tunability through thin BOX

Cited by 19 publications

References 2 publications

Influence of oxide thickness variation on analog and RF performances of SOI FinFET

Influence of oxide thickness variation on analog and RF performances of SOI FinFET

Influence of Variation in Oxide layer Thickness on Analog and RF performances of SOI FinFET

Individual analysis of inter and intragrain defects in electrically characterized polycrystalline silicon nanowire TFTs by multicomponent dark-field imaging based on nanobeam electron diffraction two-dimensional mapping

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