Experimental Study of Self-Heating Effects in Trigate Nanowire MOSFETs Considering Device Geometry

Abstract

Temperature rise by self-heating effects in nanowire (NW) transistors (NW Trs.) is systematically studied with respect to their dependence on the structural parameters. Temperature rise in NW Tr. is found to be independent of the NW size in sub-100-nm regions when compared at the same total power consumption. This is because the heat generated by the drain current is spread to the area larger than the NW channel. Dependences of temperature rise on other parameters such as gate oxide or buried oxide thickness suggest that heat dissipates mainly via source/drain or substrate not via the gate electrode.Index Terms-Self-heating effect (SHE), silicon nanowire (NW) transistor (NW Tr.), silicon on insulator (SOI).

Direct Evaluation of Self-Heating Effects in Bulk and Ultra-Thin BOX SOI MOSFETs Using Four-Terminal Gate Resistance Technique

“…Fig. 13 shows the reported R th s of bulk [7], SOI [8], [9], [11], [23], [45], and nanowire [18] MOSFETs in comparison with our results. For the bulk and thick BOX SOI MOSFETs, the measured values of R th s in our experiments are in good agreement with the trends of the previous works.…”

“…13. Relationship between R th and Lg for the previously reported devices (bulk [7], SOI [8], [9], [11], [23], [45], and nanowire [18] transistors) and measured ones in this work. t BOX of the reported devices ranges between 145 and 500 nm.…”

“…t BOX of the reported devices ranges between 145 and 500 nm. In the nanowire transistor [18], P is normalized by nanowire pitch.…”

“…AC conductance is the most popular method because of its simple measurement setup that has no specific requirements for device structures. Therefore, the AC conductance method has been widely used for the SHE evaluation of nanoscale devices including FinFETs [16] and nanowire FETs [17], [18]. However, it has been recently reported that the accuracy of the AC conductance method is questionable [19].…”

DC self-heating effects modelling in SOI and bulk FinFETs

“…Thus, for a single-finger-40-nm SOI FinFET, with 10 fins, a thermal resistance of 50 Â 10 3 K/W has been measured in [32], meanwhile our model predicts 67 Â 10 3 K/W with 50 nm long gates. In addition, for a 14-nm SOI FinFET with 120 fingers, and two fins per finger, 13 Â 10 3 K/W was obtained in [10], meanwhile our model predicts 8 Â 10 3 K/W with the gate whose length is 25 nm.…”