Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005.
DOI: 10.1109/.2005.1469250
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High-performance 50-nm-gate-length schottky-source/drain MOSFETs with dopant-segregation junctions

Abstract: High-performance operation was achieved in a novel Schottky-source/drain MOSFET (SBT: Schottky Barrier Transistor), which has dopant-segregation (DS) Schottky source/drain. Sub-100 nm complementary DS-SBTs were fabricated using the CoSi 2 process, which was fully compatible with the current CMOS technology. Excellent CMOS performance was obtained without any channel-mobility degradation, and CMOS ring oscillator was successfully demonstrated. In addition, >20 % improvement in drive current over the conventiona… Show more

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Cited by 50 publications
(26 citation statements)
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“…Unfortunately, it has been pointed out that large SB height at the source junction significantly lowers drive current [12]. Recently, a new technology, i.e., dopant-segregated SB S/D has been demonstrated to be able to overcome the shortcomings of the conventional SB S/D schemes [13][14]. Due to the high compatibility with the conventional silicided S/D scheme, the dopant-segregated NiSi SB S/D technology has attracted much attention [14][15][16].…”
Section: Introductionmentioning
confidence: 99%
“…Unfortunately, it has been pointed out that large SB height at the source junction significantly lowers drive current [12]. Recently, a new technology, i.e., dopant-segregated SB S/D has been demonstrated to be able to overcome the shortcomings of the conventional SB S/D schemes [13][14]. Due to the high compatibility with the conventional silicided S/D scheme, the dopant-segregated NiSi SB S/D technology has attracted much attention [14][15][16].…”
Section: Introductionmentioning
confidence: 99%
“…We have proposed and developed dopant-segregated Schottky S/D MOSFETs (DSS), and have demonstrated over 20% of current enhancement in DSS compared to Conv [3] . The dominant mechanism for this enhancement, however, has not been fully examined yet.…”
Section: Introductionmentioning
confidence: 99%
“…The gate oxide thickness is 1.3 nm. Deep S/D is applied to DSS to reduce junction leakage [3] . Fig.2 shows I on -I off relationship between DSS and Conv.…”
Section: Introductionmentioning
confidence: 99%
“…However, the injected carrier velocity at the source edge is limited by thermal velocity or Fermi velocity. [4][5][6] To overcome the above physical limitation, several MOSFET structures realized by source engineering, such as hot-electron transistors 7) and source-Schottky barrier structures, 8) have been proposed. In particular, in a heterojunction bipolar transistor (HBT), 9,10) a wide-gap emitter can inject higher-velocity carriers into a narrow-gap base region, using an excess kinetic energy due to the band offset at the emitter/base heterojunction.…”
Section: Introductionmentioning
confidence: 99%