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We present the FinFET process integration technology including improved sidewall transfer (SWT) process applicable to both fins and gates. Using this process, the uniform electrical characteristics of the ultra-small FinFETs of 15nm gate length and 10nm fin width have been demonstrated.A new process technique for the selective gate sidewall spacer formation (spacer formation only on the gate sidewall, no spacer on the fin sidewall) is also demonstrated for realizing low-resistance elevated source/drain (S/D) extension. IntroductionFinFETs are promising candidates for sub-20nm scale CMOS devices because of their excellent scalability [1-8]. Primary challenges for FinFETs are the formation of uniform and narrow fins and the reduction of S/D series resistance. The sidewall transfer (SWT) process was proposed to form sub-lithographic fins and reduce the line edge roughness of the fins (Fig.1) [1]. However, the integration technology for the application of SWT process to both fin and gate formation has not been reported yet. On the other hand, it is necessary to deposit silicon selectively on the narrow fins for the reduction of the series resistance by increasing the fin width in S/D regions. However, this process has been very difficult because of the residue of gate sidewall spacer material left on the fin sidewall and the agglomeration of narrow fins.In this paper, we report the FinFET process integration technology including improved SWT process applied to both fins and gates. We also present the device characteristics of the ultra-small FinFET with 15nm gate length and 10nm fin width. A new process technique for the selective gate sidewall spacer formation is also proposed and the advantages of this new approach are experimentally demonstrated.

Integration schemes of bulk FinFET SRAM cell with bulk planar FET peripheral circuit are studied for the first time. Two types of SRAM cells with different β-ratio were fabricated and investigated in the view of static noise margin (SNM). High SNM of 122 mV is obtained in the cell with 15 nm Fin width, 90 nm channel height and 20 nm gate length at V dd = 0.6 V. This is the smallest gate length FinFET SRAM reported to date.A higher beta ratio (β > 2.0) in FinFET SRAM cell will be also achieved by tuning the effective channel width of each FinFETs without area penalty by taking advantage of bulk-Si substrate.

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Device fabrication V, variability in FinFET SRAM is evaluated for the first Bulk-FinFET SRAM is used for the test devices in this time by direct measurement of the cell transistors down to 25 work. The device fabrication sequence is very similar to that in

In this paper, the physical & electrical characteristics o f ultra-thin plasma nitrided gate dielectrics are reported, aiming for sub-50 nm gate length CMOS applications. The impacts of plasma nitridation conditions on DC characteristics were investigated extensively by changing nitrogen plasma pressure, plasma immersion time, or plasma generation power. N B T l has been also investigated and the lifetime at 105C & 0.85 V operation i s estimated to be about I O years. The final current drives of 690 pA / pm for nFET and 301 pA / pm for pFET at Vdd = 0.85 V (loff = 100 nA / pm) have been achieved in sub-50 nm CMOS with optimized plasma nitrided gate dielectric with EOT

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