Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond

Kawasaki, Hiromu; Okano, K.; Kaneko, A.; Yagishita, Akira; Izumida, T.; Kondo, Takahisa; Kasai, K.; Ishida, Takeshi; Sasaki, Takahiro; Takeyama, Y.; Aoki, Naofumi; Ohtsuka, N.; Suguro, K.; Eguchi, Kazuhiro; Tsunashima, Y.; Inaba, S.; Ishimaru, K.; Ishiuchi, H.

doi:10.1109/vlsit.2006.1705221

Cited by 43 publications

(23 citation statements)

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“…As new designs use transistors with minimum size, the device variations have a large impact on cell variability. In this paper, we modeled process variations as Gaussian distribution with 3 V equal to 10% on the size and threshold voltage of transistors [22]. The simulations are performed by applying 1000 iterations of Monte Carlo simulation on SRAM cell during read operation.…”

Section: B Process Variations and Cell Failure Ratesmentioning

confidence: 99%

Hierarchical design of robust and low data dependent FinFET based SRAM array

Imani

Patil

Rosing

2015

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15)

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This paper proposes a new FinFET based SRAM cell and a cache architecture that efficiently exploits our SRAM cell for low-power and robust memory design. Our cache architecture uses invert coding scheme to encode the input data of a word line by taking into account the data composition. Based on the new data distribution, we propose two new asymmetric SRAM cells (AABG and ADWL) utilizing adaptive back-gate feedback that significantly improve cache power consumption and reliability, and provide higher performance in state-of-theart SRAM caches. The results show that the AABG cell is a good candidate for robust and low power caches, while the ADWLbased SRAM cache is low power and high performance cache. The simulations are performed on SPEC CPU 2006 benchmarks with GEM5 and HSPICE in 20nm independent gate FinFET technology. The results show that the proposed AABG (ADWL)-based cache improves static and dynamic power by at least 13% and 35% (17% and 12%) respectively, compared to other stateof-the-art cells, while guaranteeing 2.7X (1.98X) lower NBTI degradation with less than 1.5% area overhead.

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Section: B Process Variations and Cell Failure Ratesmentioning

confidence: 99%

Hierarchical design of robust and low data dependent FinFET based SRAM array

Imani

Patil

Rosing

2015

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15)

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“…However, it is very difficult to replace all transistors by FinFETs. Recently, both planar FET peripheral circuit and FinFET SRAM were fabricated on a bulk Si substrate in order to introduce FinFET to LSI fabrication early and prove that logic and SRAM FETs are unaffected by integration [5]. The fabrication process is shown in …”

Section: Gate Stackfor Finfetmentioning

confidence: 99%

“…19(b)). fin height variation [5] become a prospective device for future SoC applications. As future works, the advantage of no dopant fluctuation in FinFET SRAM hardware should be demonstrated.…”

Section: E Fin Height Tuning Techniquefor F-ratio Controlmentioning

confidence: 99%

“…The large transistor variability compromises SRAM cell stability, measured as the static noise margin (SNM). On the other hand, FinFET have attracted much attention as a candidate for scaled sub-20nm CMOS devices, and the excellent DC characteristics have been reported [1][2][3][4][5][6]. The threshold voltage variation due to the dopant fluctuation can be minimized in the FinFET because the device does not require heavy channel doping for short channel effect control.…”

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confidence: 99%

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FinFET SRAM Process Technology for hp32 nm node and beyond

Yagishita

2007

2007 IEEE International Conference on Integrated Circuit Design and Technology

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“…For example, the static noise margin of the FinFET implementation of a static RAM cell is shown to be much better than its bulk CMOS implementation [3]. However, FinFETs still face intradie and interdie process variations in a number of parameters, such as gate length, fin thickness, work function, and oxide thickness, all of which have an impact on the delay and power characteristics of FinFET logic gates, and thus the die yield.…”

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confidence: 99%

FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations

Yang

Jha

2014

IEEE Trans. VLSI Syst.

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Continued scaling of bulk CMOS technology is facing formidable challenges. FinFETs, with better control of short-channel effects, offer a promising alternative for the 22-nm technology node and beyond. However, FinFETs still suffer from process, voltage, and temperature (PVT) variations. Thus, to analyze the delay of FinFET logic circuits, statistical static timing analysis (SSTA) is more suitable than traditional static timing analysis. In this paper, using an existing SSTA algorithm as a foundation, we analyze silicon-on-insulator FinFET circuits in various new ways: 1) basing the analysis on accurate device simulation of the logic library; 2) considering voltage and temperature variations, in addition to process variations; 3) deriving accurate timing and leakage macromodels; and 4) investigating the impact of PVT variations on delay/leakage distributions at the circuit level. We propose a simplified timing model that greatly reduces the computational complexity without giving rise to any convergence issues. The timing model has an average absolute error of 3.4% and 4.4%, respectively, for gate output slope and gate delay over all logic gates and sizes, compared with accurate quasi-Monte Carlo simulations. We evaluate the performance of our SSTA algorithm with respect to Monte Carlo simulation, and extend the algorithm to enable statistical leakage and dynamic power analysis as well. We investigate the impact of PVT variations on delay/power distributions at the circuit level. We show that deterministic optimization methods can optimize both the mean and variance of circuit delay/power distributions, and even the ratio of standard deviation to mean in some cases. Finally, we show that FinFET circuits need to be carefully optimized with temperature taken into consideration, since the ratio between the leakage and dynamic power of a circuit can vary drastically depending on the operating temperature assumed.

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Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond

Cited by 43 publications

References 0 publications

Hierarchical design of robust and low data dependent FinFET based SRAM array

Hierarchical design of robust and low data dependent FinFET based SRAM array

FinFET SRAM Process Technology for hp32 nm node and beyond

FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations

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