High-Performance FinFET with Dopant-Segregated Schottky Source/Drain

Kaneko, A.; Yagishita, Akira; Yahashi, K.; Kubota, T.; Omura, Mitsuhiro; Matsuo, K.; Mizushima, Ichiro; Okano, K.; Kawasaki, H.; Izumida, T.; Kondo, Takahisa; Aoki, Naofumi; Kinoshita, Atsuhiro; Koga, J.; Inaba, S.; Ishimaru, K.; Toyoshima, Y.; Ishiuchi, H.; Suguro, K.; Eguchi, Kazuhiro; Tsunashima, Y.

doi:10.1109/iedm.2006.346926

Cited by 52 publications

(46 citation statements)

References 7 publications

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“…The most frequently used metal sillicides for the SB-S/D application include PtSi [1], [4]- [6], ErSi 2−x [1], YbSi 2−x [5], and DySi 2−x [6] due to their relatively low "natural" SB heights (SBH) to Si. With the assistance of dopant segregation, NiSi-based SB-S/D has also been successfully integrated in sub-30 nm gatelength complementary FinFETs with impressive performance [7], [8]. With PtSi of a high SBH to electrons (0.9 eV), we have, through dopant segregation [9], [10], recently succeeded in fabricatingn-channelSB-S/Dmetal-oxide-semiconductorfieldeffect-transistors (SB-MOSFETs) on ultrathin-body silicon-oninsulator (UTB-SOI) substrates [11].…”

Section: Introductionmentioning

confidence: 99%

Performance Fluctuation of FinFETs With Schottky Barrier Source/Drain

Zhang

Qiu

et al. 2008

IEEE Electron Device Lett.

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A considerable performance fluctuation of FinFETs featuring PtSi-based Schottky barrier source/drain is found. The Fin-channels measure 27-nm tall and 35-nm wide. Investigation of similarly processed transistors of broad gate-widths reveals a large variation in the position of the PtSi/Si interface with reference to the gate edge along the gate width. This variation suggests an uneven underlap between the PtSi and the gate from device to device for the FinFETs, since essentially only one silicide grain would be in contact with each Fin-channel at the PtSi/Si interface. The size of the underlap is expected to sensitively affect the performance of the FinFETs. Index Terms-FinFETs, gate underlap, MOSFETs, platinum silicide PtSi, Schottky barrier source/drain (SB-S/D), transmission electron microscopy (TEM).

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Section: Introductionmentioning

confidence: 99%

Performance Fluctuation of FinFETs With Schottky Barrier Source/Drain

Zhang

Qiu

et al. 2008

IEEE Electron Device Lett.

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“…In FinFETs [29,30] and three dimensional memory structures [31], the impurity doping onto sidewall of Si or other semiconductors is very important. Plasma doping has a potential for realizing sidewall doping, however, the doped layer coverage is not completely conformal.…”

Section: Doping For 3-dimentional Structures and Abruptness Of Dopantmentioning

confidence: 99%

Doping Technology for the Improvement of Next Generation Device Performance

Suguro

2011

AIP Conference Proceedings

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This paper reports on the ultra-rapid thermal annealing of next generation MOSFETs. In ultra-rapid thermal annealing, the most important issue is to achieve a good balance between electrical activation and impurity diffusion. Another issue of annealing implantation damages is also discussed: Optimized annealing combined with millisecond annealing and conventional halogen lamp annealing is necessary for annealing out defects at end-of range region. Application possibilities of millisecond annealing for deep junction activation and oxidation are also discussed.

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“…A 5-nm gate-all-around device has recently been reported which claims well-performing NiSi SID SB-MOSFET without dopant segregation (DS) due to 3D effects leading to additional barrier thinning [14]. demonstrated with NiSi [16] [17] and PtSi [18], all using arsenic and boron for DS. PtSi has a --0.2 eV barrier to the valence band and thus normally exhibits p-type behavior without OS.…”

Section: Introductionmentioning

confidence: 99%

“…Device design considerations For doped SID in FinFET devices the series resistance increases rapidly with the SID extension due to the high resistance of the Fin extensions. The SID series resistance can be decreased by a wrapped contact [4] or elevated SID grown by selective epitaxy [5] [6]. The elevated SID is separated to the gate by a spacer and by decreasing the spacer width the series resistance is decreased.…”

Section: Introductionmentioning

confidence: 99%

Towards Schottky-barrier source/drain MOSFETs

Östling¹,

Gudmundsson²,

Hellström³

et al. 2008

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

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Section 3. Section 4 discusses device performance and noise behavior. This paper provides an overview of metal source/drain (SID) Schottky-barrier (SB) MOSFET technology. The technology offers several benefits for scaling CMOS, Le., extremely low source/drain resistance, sharp junctions from SID to channel and low temperature processing. A successful implementation of the technology needs to overcome new obstacles such as SB height engineering and precise control of silicide growth. Device design factors such as SID to gate underlap, Si film thickness and oxide thickness affect device performance owing to their effects on the SB width. In the past two years several groups have demonstrated high-performance SB MOSFETs, which places the technology as a promising candidate for future generations of CMOS technology.

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High-Performance FinFET with Dopant-Segregated Schottky Source/Drain

Cited by 52 publications

References 7 publications

Performance Fluctuation of FinFETs With Schottky Barrier Source/Drain

Performance Fluctuation of FinFETs With Schottky Barrier Source/Drain

Doping Technology for the Improvement of Next Generation Device Performance

Towards Schottky-barrier source/drain MOSFETs

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