Direct evaluation of DC characteristic variability in FinFET SRAM Cell for 32 nm node and beyond

Inaba, S.; Kawasaki, Hiromu; Okano, K.; Izumida, T.; Yagishita, Akira; Kaneko, A.; Ishimaru, K.; Aoki, Naofumi; Toyoshima, Y.

doi:10.1109/iedm.2007.4418980

Cited by 21 publications

(13 citation statements)

References 3 publications

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“…[4][5][6] There has been extensive study on RDD and a combination impact on FinFET with other variation sources, such as line edge roughness, work function variation and random interface traps. [7][8][9][10][11][12][13][14][15] However, most of the study has focused on the random dopants induced fluctuation in the channel region no matter it is doped or intrinsic with lateral dopants diffusing from the extension region, which can be referred as gatesource/drain (G-S/D) overlap. The RDD effect in extension region has not drawn enough attention.…”

Section: Introductionmentioning

confidence: 99%

Impact of random discrete dopant in extension induced fluctuation in gate–source/drain underlap FinFET

Wang

Huang

Zhang

et al. 2014

Jpn. J. Appl. Phys.

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In this work, three dimensional technology computer-aided design (TCAD) simulations are performed to investigate the impact of random discrete dopant (RDD) including extension induced fluctuation in 14 nm silicon-on-insulator (SOI) gate–source/drain (G–S/D) underlap fin field effect transistor (FinFET). To fully understand the RDD impact in extension, RDD effect is evaluated in channel and extension separately and together. The statistical variability of FinFET performance parameters including threshold voltage (V th), subthreshold slope (SS), drain induced barrier lowering (DIBL), drive current (I on), and leakage current (I off) are analyzed. The results indicate that RDD in extension can lead to substantial variability, especially for SS, DIBL, and I on and should be taken into account together with that in channel to get an accurate estimation on RDF. Meanwhile, higher doping concentration of extension region is suggested from the perspective of overall variability control.

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Section: Introductionmentioning

confidence: 99%

Impact of random discrete dopant in extension induced fluctuation in gate–source/drain underlap FinFET

Wang

Huang

Zhang

et al. 2014

Jpn. J. Appl. Phys.

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“…With increased device variability in nanometer scale technologies, static random-access memories (SRAMs) become more and more vulnerable to noise sources [1]. This is particularly true for sixtransistor cell (6 T) SRAMs that continue playing a dominant role in future technology generations given its combination of density, performance, and compatibility with standard fabrication processes.…”

Section: Introductionmentioning

confidence: 99%

Alternate characterization technique for static random‐access memory static noise margin determination

Merino

Bota

Picos

et al. 2012

Circuit Theory & Apps

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The cell static noise margin (SNM) is widely used as a stability criterion for static random-access memory cells design. This parameter is typically determined through electrical simulations since direct experimental characterization of SNM is not achievable.In this work, we present a methodology that provides an indirect measurement of the SNM on a per-cell basis for six-transistor SRAMs. It is based on combining an Adaptive Neuro-Fuzzy Inference System (ANFIS) with circuit-level cell experimentally measurable parameters as input variables to the tool. We show that it is possible to obtain the SNM for individual memory cells using the same experimental setup and data than that required for shmoo plot measurements. Results confirm that the SNM can be experimentally estimated with a relative error compared with electrical simulations that is below 0.5%.

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“…Multi-gate field-effect transistor (MuGFET) devices with the conduction channels wrapped around silicon fins (FinFETbased MuGFET devices) are considered one of the most promising device architectures for enabling further complementary metal-oxide-semiconductor (CMOS) scaling beyond the 32 nm technology node, thanks to their improved electrostatics and steeper sub-threshold slopes (SS), with reduced threshold voltage (V T ) variability due to lower channel dopants concentration. [1][2][3][4][5][6][7][8][9][10][11][12][13] This makes them particularly attractive for helping prolong static random access memory (SRAM) scaling, facing ever-increasingly challenges with maintaining acceptable noise margins and controlled instability. However, FinFET parasitics remain a concern, requiring reduction of the series resistance R SD through improved fin morphology and fin doping.…”

Section: Introductionmentioning

confidence: 99%

Multi-Gate Fin Field-Effect Transistors Junctions Optimization by Conventional Ion Implantation for (Sub-)22 nm Technology Nodes Circuit Applications

Veloso

Keersgieter

Brus

et al. 2011

Jpn. J. Appl. Phys.

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In this work we explore several doping schemes for aggressively scaled multi-gate field-effect transistor devices with the conduction channels wrapped around silicon fins (FinFETs) (H Fin∼37 nm, W Fin≥10 nm, L g≥30 nm), using conventional ion implantation (I/I), and suitable for both logic and dense circuit applications. We demonstrate that low-energy and: 1) low-tilt, double-sided extension(-less) I/I, or 2) high-tilt, single-sided extension I/I schemes can enable pitch scaling without resist shadowing effects, with no penalty in device performance and yielding higher six transistors-static random access memory (6T-SRAM) static noise margin (SNM) values. Key advantages of the extension-less approach are: reduced cost and cycle time with 2 less critical I/I photos, enabling better quality, defect-free growth of Si-epitaxial raised source/drain (SEG), and up to 20× lower I OFF. It, however, requires a tight spacer critical dimension (CD) control, a less critical parameter for the single-sided I/I scheme, which also allows wider overlay margins.

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Direct evaluation of DC characteristic variability in FinFET SRAM Cell for 32 nm node and beyond

Abstract: Device fabrication V, variability in FinFET SRAM is evaluated for the first Bulk-FinFET SRAM is used for the test devices in this time by direct measurement of the cell transistors down to 25 work. The device fabrication sequence is very similar to that in

Cited by 21 publications

References 3 publications

Impact of random discrete dopant in extension induced fluctuation in gate–source/drain underlap FinFET

Impact of random discrete dopant in extension induced fluctuation in gate–source/drain underlap FinFET

Alternate characterization technique for static random‐access memory static noise margin determination

Multi-Gate Fin Field-Effect Transistors Junctions Optimization by Conventional Ion Implantation for (Sub-)22 nm Technology Nodes Circuit Applications

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