Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension

Abstract

We present the FinFET process integration technology including improved sidewall transfer (SWT) process applicable to both fins and gates. Using this process, the uniform electrical characteristics of the ultra-small FinFETs of 15nm gate length and 10nm fin width have been demonstrated.A new process technique for the selective gate sidewall spacer formation (spacer formation only on the gate sidewall, no spacer on the fin sidewall) is also demonstrated for realizing low-resistance elevated source/drain (S/D) extension. IntroductionFinFETs are promising candidates for sub-20nm scale CMOS devices because of their excellent scalability [1-8]. Primary challenges for FinFETs are the formation of uniform and narrow fins and the reduction of S/D series resistance. The sidewall transfer (SWT) process was proposed to form sub-lithographic fins and reduce the line edge roughness of the fins (Fig.1) [1]. However, the integration technology for the application of SWT process to both fin and gate formation has not been reported yet. On the other hand, it is necessary to deposit silicon selectively on the narrow fins for the reduction of the series resistance by increasing the fin width in S/D regions. However, this process has been very difficult because of the residue of gate sidewall spacer material left on the fin sidewall and the agglomeration of narrow fins.In this paper, we report the FinFET process integration technology including improved SWT process applied to both fins and gates. We also present the device characteristics of the ultra-small FinFET with 15nm gate length and 10nm fin width. A new process technique for the selective gate sidewall spacer formation is also proposed and the advantages of this new approach are experimentally demonstrated.

A pragmatic design methodology using proper isolation and doping for bulk FinFETs

“…Then, the gate oxide is formed by dry oxidation in furnace. After gate oxidation, the gateto-substrate isolation oxide could be deposited by high density plasma chemical vapor deposition (HDPCVD) as STI formation [11], [12]. Therefore, the thicknesses of isolation oxide and top-gate oxide are about the same as shown in inset of Fig.…”

Challenges of 22 nm and beyond CMOS technology

“…IBM has fabricated and investigated FINFET devices with traditional gate stack for the 22 nm technology node and estimated the weakness from capacitance point of view, with a Cgs minimizing scheme proposed [122] . Fin patterning based on spacer technology has been proposed for fine Fin control [117] . Novel SiBCN low K spacer technology and spacer removal method have been demonstrated as examples for parasitic capacitance reduction [124,125] .…”

CMP—The Next Fifteen Years

“…Many of these papers discuss the use of CMP in the fabrication of Finfets. Figure 20.11 [9] shows how Toshiba researchers use CMP to planarize the surface between fin formation and gate formation. Planarization here is required in order to provide a uniform depth of focus for polygate lithography.…”